Altera Low Latency Ethernet 10G MAC - Manual (Page 23)

Functional Description of LL Ethernet 10G MAC
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2014.12.15
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The Low Latency (LL) Ethernet 10G MAC IP core handles the flow of data between a client and an
Ethernet network through an Ethernet PHY. On the transmit path, the MAC IP core accepts client frames
and constructs Ethernet frames by inserting various control fields, such as checksums before forwarding
them to the PHY. Similarly, on the receive path, the MAC accepts Ethernet frames via a PHY, performs
checks, and removes the relevant fields before forwarding the frames to the client. You can configure the
MAC IP core to collect statistics on both transmit and receive paths.
Architecture
The LL Ethernet 10G MAC IP core is a composition of the following blocks: MAC receiver (MAC RX),
MAC transmitter (MAC TX), configuration and status registers, and clock and reset.
Figure 3-1: LL Ethernet 10G MAC Block Diagram
MAC TX
Control & Status
Registers
MAC RX
Clock & Reset
LL Ethernet 10G MAC
CSR Adapter
(Optional)
Av
alon-ST 32/64b A
dapt
er
(O
ptional)
XGMII SDR 32/64b A
dapt
er
(O
ptional)
32-Bit XGMII Transmit Interface
8-Bit GMII Transmit Interface
4-Bit MII Transmit Interface
32-Bit XGMII Receive Interface
8-Bit GMII Receive Interface
4-Bit MII Receive Interface
64-Bit XGMII
Receive Interface
64-Bit XGMII
Transmit Interface
64-Bit XGMII
Receive Interface
64-Bit XGMII
Transmit Interface
Flow
Control
Link
Fault
Respective
Domains
Clock & Reset
Signals Clock & Reset
Signals
Clock & Reset
Signals
32-Bit Avalon-ST
Transmit Interface
32-Bit Avalon-MM
Interface
32-Bit Avalon-ST
Receive Interface
Notes:
(1) Applies to 1G/10G and Multi Speed MAC only.
(2) Applies to Multi Speed MAC only.
(1)
(1)
(2)
(2)
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