Altera Low Latency Ethernet 10G MAC User Manual
Page 104
Signal
Direction
Width
Description
tx_etstamp_ins_ctrl_ingress_
timestamp_96b[]
In
96
96-bit format of ingress timestamp.
(48 bits second + 32 bits nanosecond
+ 16 bits fractional nanosecond)
.Assert this signal in the same clock
cycle as the start of packet (avalon_
st_tx_startofpacket is asserted).
tx_etstamp_ins_ctrl_ingress_
timestamp_64b[]
In
64
64-bit format of ingress timestamp.
(48-bits nanosecond + 16-bits
fractional nanosecond). Assert this
signal in the same clock cycle as the
start of packet (avalon_st_tx_startof‐
packet is asserted).
tx_etstamp_ins_ctrl_residence_
time_calc_format
In
1
Format of timestamp to be used for
residence time calculation. 0: 96-bits
(96-bits egress timestamp - 96-bits
ingress timestamp). 1: 64-bits (64-bits
egress timestamp - 64-bits ingress
timestamp). Assert this signal in the
same clock cycle as the start of packet
(avalon_st_tx_startofpacket is
asserted).
tx_etstamp_ins_ctrl_checksum_
zero
In
1
Assert this signal to set the checksum
field of UDP/IPv4 to zero. Required
offset location of checksum field.
Assert this signal in the same clock
cycle as the start of packet (avalon_
st_tx_startofpacket is asserted).
tx_etstamp_ins_ctrl_checksum_
correct
In
1
Assert this signal to correct UDP/
IPv6 packet checksum, by updating
the checksum correction, which is
specified by checksum correction
offset. Required offset location of
checksum correction. Assert this
signal in the same clock cycle as the
start of packet (avalon_st_tx_startof‐
packet is asserted).
tx_etstamp_ins_ctrl_offset_
timestamp[]
In
16
The location of the timestamp field,
relative to the first byte of the packet.
Assert this signal in the same clock
cycle as the start of packet (avalon_
st_tx_startofpacket is asserted).
tx_etstamp_ins_ctrl_offset_
correction_field[]
In
16
The location of the correction field,
relative to the first byte of the packet.
Assert this signal in the same clock
cycle as the start of packet (avalon_
st_tx_startofpacket is asserted).
5-22
IEEE 1588v2 Egress Transmit Signals
UG-01144
2014.12.15
Altera Corporation
Interface Signals for LL Ethernet 10G MAC