Figure 3-25: ptp packet over udp/ipv6 – Altera Low Latency Ethernet 10G MAC User Manual
Page 52
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Figure 3-25: PTP Packet over UDP/IPv6
Version | Traffic Class | Flow Label
Payload Length
4 Octet
2 Octets
Source IP Address
16 Octets
Destination IP Address
16 Octets
Source Port
2 Octets
Destination Port = 319 / 320
2 Octets
Hop Limit
Next Header = 0x11
1 Octet
1 Octet
Length/Type = 0x86DD
Source Address
Destination Address
2 Octets
6 Octets
6 Octets
Checksum
Length
2 Octets
2 Octets
flagField
correctionField
transportSpecific | messageType
reserved | versionPTP
reserved
1 Octet
1 Octet
1 Octet
2 Octets
8 Octets
reserved
4 Octets
SourcePortIdentify
10 Octets
sequenceId
2 Octets
controlField
1 Octet
logMessageInterval
1 Octet
TimeStamp
Payload
10 Octets
0..1500/9600 Octets
extended bytes
2 Octets
CRC
Note:
(1) For packets with VLAN or Stacked VLAN tag, add 4 or 8 octets offsets before the length/type field.
4 Octets
domainNumber
messageLength
2 Octets
1 Octet
MAC Header
UDP Header
IP Header
PTP Header
(1)
3-30
PTP Packet over UDP/IPv6
UG-01144
2014.12.15
Altera Corporation
Functional Description of LL Ethernet 10G MAC
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)