Altera Low Latency Ethernet 10G MAC - Manual (Page 87)

Signal Direction Width Description
csr_read
In 1 Assert this signal to request a read.
csr_readdata[]
Out 32 Data read from the specified register. The data is
valid when the
csr_waitrequest
signal is
deasserted.
csr_write
In 1 Assert this signal to request a write.
csr_writedata[]
In 32 Data to be written to the specified register. The data
is written when the
csr_waitrequest
signal is
deasserted.
csr_waitrequest
Out 1
When asserted, this signal indicates that the MAC
IP core is busy and not ready to accept any read or
write requests.
• When you have requested for a read or write,
keep the control signals to the Avalon-MM
interface constant while this signal is asserted.
The request is complete when it is deasserted.
• This signal can be high or low during idle cycles
and reset. Therefore, the user application must
not make any assumption of its assertion state
during these periods.
Avalon-ST Data Interfaces
Avalon-ST TX Data Interface Signals
Table 5-6: Avalon-ST TX Data Interface Signals
Signal Direction Width Description
avalon_st_tx_
startofpacket
In 1 Assert this signal to indicate the beginning of the
TX data on the Avalon-ST interface.
avalon_st_tx_
endofpacket
In 1 Assert this signal to indicate the end of the TX data
on the Avalon-ST interface.
avalon_st_tx_valid
In 1 Assert this signal to indicate that
avalon_st_tx_
data[]
and other signals on this interface are valid.
avalon_st_tx_ready
Out 1 When asserted, indicates that the MAC IP core is
ready to accept data. The reset value for this signal
is 1'b1. However, the user logic should not rely on
this default reset behavior to operate.
avalon_st_tx_error
In 1 Assert this signal to indicate that the current TX
packet contains errors.
avalon_st_tx_data[]
In 32 TX data from the client.
UG-01144
2014.12.15
Avalon-ST Data Interfaces 5-5
Interface Signals for LL Ethernet 10G MAC Altera Corporation
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