Altera Low Latency Ethernet 10G MAC User Manual
Page 78
Memory-based statistics counters may not be accurate when the MAC IP core receives or transmits back-
to-back undersized frames. On the TX datapath, you can enable padding to avoid this situation.
Undersized frames are frames with less than 64 bytes.
Table 4-19: TX and RX Statistics Registers
Word
Offset
Register Name
Description
Access
HW Reset
Value
0x0140
tx_stats_clr
• Bit 0—Set this register to 1 to clear
all TX statistics counters.
• Bits 31:1—reserved.
RW1C
0x0
0x01C0
rx_stats_clr
• Bit 0—Set this register to 1 to clear
all RX statistics counters.
• Bits 31:1—reserved.
RW1C
0x0
0x0142
tx_stats_framesOK
36-bit statistics counter that collects
the number of frames that are
successfully received or transmitted,
including control frames.
RO
0x0
0x0143
0x01C2
rx_stats_framesOK
0x01C3
0x0144
tx_stats_framesErr
36-bit statistics counter that collects
the number of frames received or
transmitted with error, including
control frames.
RO
0x0
0x0145
0x01C4
rx_stats_framesErr
0x01C5
0x0146
tx_stats_framesCRCErr
36-bit statistics counter that collects
the number of frames received or
transmitted with CRC error.
RO
0x0
0x0147
0x01C6
rx_stats_framesCRCErr
0x01C7
0x0148
tx_stats_octetsOK
Statistics counter that collects the
payload length, including the bytes in
control frames. The payload length is
the number of data and padding bytes
received or transmitted. If the
tx_
vlan_detection[0]
or
rx_vlan_
detection[0]
register bit is set to 1,
the VLAN and stacked VLAN tags are
counted as part of the TX payload or
RX payload respectively.
RO
0x0
0x0149
0x01C8
rx_stats_octetsOK
0x01C9
4-26
Statistics Registers
UG-01144
2014.12.15
Altera Corporation
Configuration Registers for LL Ethernet 10G MAC