Altera Low Latency Ethernet 10G MAC - Manual (Page 93)

Signal Direction Width Description
avalon_st_rxstatus_
data[]
Out 40
Contains information about the RX frame.
• Bits 0 to 15: Payload length.
• Bits 16 to 31: Packet length.
• Bit 32: When set to 1, indicates a stacked VLAN
frame. Ignore this bit when the MAC is
configured not to detect stacked VLAN frames
(
tx_vlan_detection[0]
= 1).
• Bit 33: When set to 1, indicates a VLAN frame.
Ignore this bit when the MAC is configured not
to detect VLAN frames (
tx_vlan_
detection[0]
= 1).
• Bit 34: When set to 1, indicates a control frame.
• Bit 35: When set to 1, indicates a pause frame.
• Bit 36: When set to 1, indicates a broadcast
frame.
• Bit 37: When set to 1, indicates a multicast
frame.
• Bit 38: When set to 1, indicates a unicast frame.
• Bit 39: When set to 1, indicates a PFC frame.
avalon_st_rxstatus_
error[]
Out 7
When set to 1, the respective bit indicates the
following error type in the RX frame.
• Bit 0: Undersized frame.
• Bit 1: Oversized frame.
• Bit 2: Payload length error.
• Bit 3: CRC error.
• Bit 4: Unused.
• Bit 5: Unused.
• Bit 6: PHY error.
The IP core presents the error status on this bus in
the same clock cycle it asserts the
avalon_st_
rxstatus_valid
signal. The error status is invalid
when an overflow occurs.
avalon_st_rx_pfc_
status_valid
Out 1 When asserted, this signal qualifies the
avalon_st_
rx_pfc_status_data[]
signal.
UG-01144
2014.12.15
Avalon-ST RX Status Signals 5-11
Interface Signals for LL Ethernet 10G MAC Altera Corporation
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