Altera Low Latency Ethernet 10G MAC - Manual (Page 94)

Signal Direction Width Description
avalon_st_rx_pfc_
status_data[]
Out n
(4 - 16)
n = 2 x Number of PFC queues parameter
When set to 1, the respective bit indicates the
following flow control request from the remote
partner.
• Bit 0: XON request for priority queue 0.
• Bit 1: XOFF request for priority queue 0.
• Bit 2: XON request for priority queue 1.
• Bit 3: XOFF request for priority queue 1.
• Bit 4: XON request for priority queue 2.
• Bit 5: XOFF request for priority queue 2.
• .. and so forth.
Related Information
Length Checking on page 3-14
Describes how the MAC IP core checks the frame and payload lengths.
PHY-side Interfaces
XGMII TX Signals
Table 5-11: XGMII TX Signals
Signal Condition Direction Width Description
xgmii_tx_
data[]
Use legacy Ethernet
10G MAC XGMII
interface disabled.
Enable 10GBASE-R
register mode
disabled.
Out 32
4-lane data bus. Lane 0 starts from the
least significant bit.
• Lane 0:
xgmii_tx_data[7:0]
• Lane 1:
xgmii_tx_data[15:8]
• Lane 2:
xgmii_tx_data[23:16]
• Lane 3:
xgmii_tx_data[31:24]
Use legacy Ethernet
10G MAC XGMII
interface disabled.
Enable 10GBASE-R
register mode
enabled.
Out 64
8-lane SDR XGMII transmit data. This
signal connects directly to the
NativePHY IP core.
• Lane 0:
xgmii_tx_data[7:0]
• Lane 1:
xgmii_tx_data[15:8]
• Lane 2:
xgmii_tx_data[23:16]
• Lane 3:
xgmii_tx_data[31:24]
• Lane 4:
xgmii_tx_data[39:32]
• Lane 5:
xgmii_tx_data[47:40]
• Lane 6:
xgmii_tx_data[55:48]
• Lane 7:
xgmii_tx_data[63:56]
5-12 PHY-side Interfaces
UG-01144
2014.12.15
Altera Corporation Interface Signals for LL Ethernet 10G MAC
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