Altera Low Latency Ethernet 10G MAC - Manual (Page 83)

Interface Signals for LL Ethernet 10G MAC
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2014.12.15
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Interfaces on page 3-2
Overview of the interfaces and signals.
Clock and Reset Signals
The LL Ethernet 10G MAC IP core operates in multiple clock domains. You can use different sources to
drive the clock and reset domains. You can also use the same clock source as specified in the description
of each signal.
Table 5-1: Clock and Reset Signals
Signal Operating
Mode
Direction Width Description
tx_312_5_clk
10G, 1G/10G,
10M/100M/
1G/10G
In 1 312.5-MHz clock for the MAC TX
datapath when the Enable
10GBASE-R register mode is
disabled. You may use the same
clock source for this clock and
rx_
312_5_clk
.
tx_xcvr_clk
10G In 1 322.265625-MHz clock for the MAC
TX datapath when the Enable
10GBASE-R register mode is
enabled.
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