Teledyne LeCroy X-STREAM OSCILLOSCOPES Remote Control - Manual (Page 69)

WM-RCM-E Rev D ISSUED: February 2005
63
C H A P T E R F I V E
Checking Waveform Status
Use Status Registers
A wide range of status registers allows you to quickly determine the instrument's internal processing status at
any time. These registers and the oscilloscope’s status reporting system, which group related functions together,
are designed to comply with IEEE 488.2 recommendations. Some, such as the Status Byte Register (STB) or
the Standard Event Status Register (ESR), are required by the IEEE 488.2 Standard. Others are device specific,
including the Command Error Register (CMR) and Execution Error Register (EXR). Those commands
associated with IEEE 488.2 mandatory status registers are preceded by an asterisk (*).
OVERVIEW
The Standard Event Status Bit (ESB) and the Internal Status Change Bit (INB) in the STB are summary bits of
the ESR and the Internal State Change Register (INR). The Message Available Bit (MAV) is set whenever there
are data bytes in the output queue. The Value Adapted Bit (VAB) indicates that a parameter value was adapted
during a previous command interpretation. For example, if the command TDIV 2.5 US was received, the
timebase would be set to 2 ms/div along with the VAB bit.
The Master Summary Status bit (MSS) indicates a request for service from the oscilloscope. You can only set
the MSS bit if you have enabled one or more of the other STB bits with the Service Request Enable Register
(SRE).
All Enable registers (SRE, ESE, and INE) are used to generate a bit-wise AND with their associated status
registers. The logical OR of this operation is reported to the STB register. At power-on, all Enable registers are
zero, inhibiting any reporting to the STB.
The ESR primarily summarizes errors, whereas the INR reports internal changes to the instrument. Additional
details of errors reported by ESR can be obtained with the queries CMR?, DDR?, EXR?, and URR?.
The register structure contains one additional register, not shown on the next page (Fig.1). This is the Parallel
Poll Enable Register (PRE), which behaves exactly like the SRE but sets the “ist” bit used in the Parallel Poll.
Read the “ist” bit with the *IST? query.
Example: If you were to send the erroneous command TRIG_MAKE SINGLE to your instrument, the
oscilloscope would reject it and set the Command Error Register (CMR) to the value 1 (unrecognized
command/query header). The non-zero value of CMR would be reported to Bit 5 of the Standard Event
Status Register (ESR), which is then set. Nothing further would occur unless the corresponding Bit 5 of the
Standard Event Status Enable Register (ESE) was set with the command *ESE 32, enabling Bit 5 of ESR to be
set for reporting to the summary bit ESB of the STB.