Rainbow Electronics DS3131 - Manual (Page 94)

DS3131
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- FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD -
dword 0; Bits 0 to 31/Current Data Buffer Address. The current 32-bit address of the data buffer that is being
used. This address is used by the DMA to keep track of where data should be written to as it comes in from the
receive FIFO.
- FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD -
dword 1; Bits 0 to 15/Current Descriptor Pointer. This 16-bit value is the offset from the receive descriptor
base address of the current receive descriptor being used by the DMA to describe the specifics of the data stored in
the associated data buffer.
- FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD -
dword 1; Bits 16 to 31/Starting Descriptor Pointer. This 16-bit value is the offset from the receive descriptor
base address of the first receive descriptor in a link-list chain of descriptors. This pointer is written into the done
queue by the DMA after a specified number of data buffers (see the threshold value below) have been filled.
- HOST MUST CONFIGURE -
dword 2; Bit 0/Channel Enable (CHEN). This bit is controlled by the host to enable and disable an HDLC
channel.
0 = HDLC channel disabled
1 = HDLC channel enabled
- HOST MUST CONFIGURE -
dword 2; Bits 1, 2/Buffer Size Select. These bits are controlled by the host to select the manner in which the
receive DMA stores incoming packet data.
00 = use large size data buffers only
01 = use small size data buffers only
10 = fill a small buffer first, followed then by large buffers as needed
11 = illegal state and should not be selected
- HOST MUST CONFIGURE -
dword 2; Bits 3 to 6/Buffer Offset. These bits are controlled by the host to determine if the packet data written
into the first data buffer should be offset by up to 15 Bytes. This allows the host complete control over the manner
in which data is written into main memory.
0000 (0h) = 0-Byte offset from the data buffer address of the first data buffer
0001 (1h) = 1-Byte offset from the data buffer address of the first data buffer
1111 (Fh) = 15-Byte offset from the data buffer address of the first data buffer
- HOST MUST CONFIGURE -
dword 2; Bits 7 to 9/Threshold. These bits are controlled by the host to determine when the DMA should write
into the done queue that data is available for processing. For transparent mode (RTRANS = 1), the three threshold
bits must not be set to ‘000.’
000 = DMA should write to the done queue only after packet reception is complete
001 = DMA should write to the done queue after 1 data buffer has been filled
010 = DMA should write to the done queue after 2 data buffers have been filled
011 = DMA should write to the done queue after 3 data buffers have been filled
100 = DMA should write to the done queue after 4 data buffers have been filled
101 = DMA should write to the done queue after 5 data buffers have been filled
110 = DMA should write to the done queue after 6 data buffers have been filled
111 = DMA should write to the done queue after 7 data buffers have been filled