Rainbow Electronics DS3131 - Manual (Page 2)

DS3131
2 of 174
TABLE OF CONTENTS
1. MAIN FEATURES .......................................................................................................................... 6
2. DETAILED DESCRIPTION .......................................................................................................... 7
3. SIGNAL DESCRIPTION.............................................................................................................. 14
3.1 O VERVIEW /S IGNAL L IST .......................................................................................................................... 14
3.2 S ERIAL P ORT I NTERFACE S IGNAL D ESCRIPTION ..................................................................................... 20
3.3 L OCAL B US S IGNAL D ESCRIPTION .......................................................................................................... 20
3.4 JTAG S IGNAL D ESCRIPTION ................................................................................................................... 23
3.5 PCI B US S IGNAL D ESCRIPTION ............................................................................................................... 24
3.6 PCI E XTENSION S IGNALS ........................................................................................................................ 26
3.7 S UPPLY AND T EST S IGNAL D ESCRIPTION ................................................................................................ 27
4. MEMORY MAP ............................................................................................................................ 28
4.1 I NTRODUCTION ........................................................................................................................................ 28
4.2 G ENERAL C ONFIGURATION R EGISTERS (0 XX ) ........................................................................................ 28
4.3 R ECEIVE P ORT R EGISTERS (1 XX ) ............................................................................................................ 29
4.4 T RANSMIT P ORT R EGISTERS (2 XX ).......................................................................................................... 30
4.5 R ECEIVE HDLC C ONTROL R EGISTERS (3 XX ) ......................................................................................... 31
4.6 T RANSMIT HDLC C ONTROL R EGISTERS (4 XX )....................................................................................... 32
4.7 BERT R EGISTERS (5 XX ).......................................................................................................................... 33
4.8 R ECEIVE DMA R EGISTERS (7 XX )............................................................................................................ 33
4.9 T RANSMIT DMA R EGISTERS (8 XX )......................................................................................................... 34
4.10 FIFO R EGISTERS (9 XX ) ........................................................................................................................... 34
4.11 PCI C ONFIGURATION R EGISTERS FOR F UNCTION 0 (PIDSEL/A XX ) ...................................................... 35
4.12 PCI C ONFIGURATION R EGISTERS FOR F UNCTION 1 (PIDSEL/B XX )....................................................... 35
5. GENERAL DEVICE CONFIGURATION AND STATUS/INTERRUPT............................... 36
5.1 M ASTER R ESET AND ID R EGISTER D ESCRIPTION ................................................................................... 36
5.2 M ASTER C ONFIGURATION R EGISTER D ESCRIPTION ................................................................................ 37
5.3 S TATUS AND I NTERRUPT ......................................................................................................................... 39
5.3.1 General Description of Operation ...................................................................................................... 39
5.3.2 Status and Interrupt Register Description........................................................................................... 41
5.4 T EST R EGISTER D ESCRIPTION ................................................................................................................. 46
6. LAYER 1......................................................................................................................................... 47
6.1 G ENERAL D ESCRIPTION ........................................................................................................................... 47
6.2 P ORT R EGISTER D ESCRIPTIONS ............................................................................................................... 49
6.3 BERT ....................................................................................................................................................... 51
6.4 BERT R EGISTER D ESCRIPTION ............................................................................................................... 52
7. HDLC .............................................................................................................................................. 59
7.1 G ENERAL D ESCRIPTION ........................................................................................................................... 59
7.2 HDLC O PERATION .................................................................................................................................. 59
7.3 B IT -S YNCHRONOUS HDLC R EGISTER D ESCRIPTION .............................................................................. 61
8. FIFO ................................................................................................................................................ 65
8.1 G ENERAL D ESCRIPTION AND E XAMPLE .................................................................................................. 65
8.1.1 Receive High Watermark .................................................................................................................... 67
8.1.2 Transmit Low Watermark.................................................................................................................... 67
8.2 FIFO R EGISTER D ESCRIPTION ................................................................................................................. 68
9. DMA ................................................................................................................................................ 74
9.1 I NTRODUCTION ........................................................................................................................................ 74
9.2 R ECEIVE S IDE .......................................................................................................................................... 76
9.2.1 Overview ............................................................................................................................................. 76
9.2.2 Packet Descriptors .............................................................................................................................. 80
9.2.3 Free Queue.......................................................................................................................................... 82