Rainbow Electronics DS3131 - Manual (Page 86)

DS3131
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Register Name:
RDMAQ
Register Description:
Receive DMA Queues Control
Register Address: 0780h
Bit
# 7 6 5 4 3 2 1 0
Name reserved reserved RDQF RDQFE RFQSF RFQLF reserved RFQFE
Default 0 0 0 0 0 0 0 0
Bit # 15 14 13 12 11 10 9 8
Name reserved reserved reserved reserved reserved RDQT2 RDQT1 RDQT0
Default 0 0 0 0 0 0 0 0
Note: Bits that are underlined are read-only; all other bits are read-write.
Bit 0/Receive Free-Queue FIFO Enable (RFQFE). To enable the DMA to burst read descriptors from the free
queue, this bit must be set to 1. If this bit is set to 0, descriptors are read one at a time.
0 = free queue burst read disabled
1 = free queue burst read enabled
Bit 2/Receive Free-Queue Large Buffer FIFO Flush (RFQLF). When this bit is set to 1, the internal large
buffer free queue FIFO is flushed (currently loaded free-queue descriptors are lost). This bit must be set to 0 for
proper operation.
0 = FIFO in normal operation
1 = FIFO is flushed
Bit 3/Receive Free-Queue Small Buffer FIFO Flush (RFQSF). When this bit is set to 1, the internal small
buffer free-queue FIFO is flushed (currently loaded free-queue descriptors are lost). This bit must be set to 0 for
proper operation.
0 = FIFO in normal operation
1 = FIFO is flushed
Bit 4/Receive Done-Queue FIFO Enable (RDQFE). See Section
9.2.4 for details.
Bit 5/Receive Done-Queue FIFO Flush (RDQF). See Section
9.2.4 for details.
Bits 8 to 10/Receive Done-Queue Status Bit Threshold Setting (RDQT0 to RDQT2). See Section
9.2.4 for
details.