Rainbow Electronics DS3131 - Manual (Page 92)

DS3131
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Bit 5/Receive Done-Queue FIFO Flush (RDQF). When this bit is set to 1, the internal done-queue FIFO is
flushed by sending all data into the done queue. This bit must be set to 0 for proper operation.
0 = FIFO in normal operation
1 = FIFO is flushed
Bits 8 to 10/Receive Done-Queue Status-Bit Threshold Setting (RDQT0 to RDQT2). These bits determine
when the DMA sets the receive DMA done-queue write (RDQW) status bit in the status register for DMA
(SDMA) register.
000 = set the RDQW status bit after each descriptor write to the done queue
001 = set the RDQW status bit after 2 or more descriptors are written to the done queue
010 = set the RDQW status bit after 4 or more descriptors are written to the done queue
011 = set the RDQW status bit after 8 or more descriptors are written to the done queue
100 = set the RDQW status bit after 16 or more descriptors are written to the done queue
101 = set the RDQW status bit after 32 or more descriptors are written to the done queue
110 = set the RDQW status bit after 64 or more descriptors are written to the done queue
111 = set the RDQW status bit after 128 or more descriptors are written to the done queue