Rainbow Electronics DS3131 - Manual (Page 5)

DS3131
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Figure 11-9. 8-Bit Read Cycle ................................................................................................................. 151
Figure 11-10. 8-Bit Write Cycle .............................................................................................................. 152
Figure 11-11. 16-Bit Read Cycle ............................................................................................................. 153
Figure 11-12. 8-Bit Write Cycle .............................................................................................................. 154
Figure 12-1. Block Diagram .................................................................................................................... 155
Figure 12-2. TAP Controller State Machine ............................................................................................ 156
Figure 13-1. Layer 1 Port AC Timing Diagram....................................................................................... 162
Figure 13-2. Local Bus Bridge Mode (LMS = 0) AC Timing Diagram .................................................. 163
Figure 13-3. Local Bus Configuration Mode (LMS = 1) AC Timing Diagrams..................................... 165
Figure 13-4. PCI Bus Interface AC Timing Diagram .............................................................................. 167
Figure 13-5. JTAG Test Port Interface AC Timing Diagram .................................................................. 168
Figure 15-1. 28 T1 Lines Demuxed from a T3 Line................................................................................ 170
Figure 15-2. Multiport T1 or E1 Application .......................................................................................... 171
Figure 15-3. Unchannelized T3 or E3 Application.................................................................................. 172
Figure 15-4. DSLAM/Cable Modem Application ................................................................................... 173
Figure 15-5. SONET/SDH Overhead Termination Application.............................................................. 174
LIST OF TABLES
Table 1-A. Data Sheet Definitions ............................................................................................................... 7
Table 2-A. Restrictions .............................................................................................................................. 12
Table 2-B. Initialization Steps ................................................................................................................... 13
Table 2-C. Indirect Registers ..................................................................................................................... 13
Table 3-A. Signal Description ................................................................................................................... 14
Table 4-A. Memory Map Organization ..................................................................................................... 28
Table 6-A. HDLC Channel Assignment .................................................................................................... 47
Table 6-B. Port Configuration Options...................................................................................................... 47
Table 7-A. HDLC Channel Assignment .................................................................................................... 59
Table 7-B. Receive Bit-Synchronous HDLC Packet Processing Outcomes ............................................. 60
Table 7-C. Receive Bit-Synchronous HDLC Functions ............................................................................ 60
Table 7-D. Transmit Bit-Synchronous HDLC Functions .......................................................................... 61
Table 8-A. FIFO Priority Algorithm Select ............................................................................................... 65
Table 9-A. DMA Registers to be Configured by the Host on Power-Up .................................................. 75
Table 9-B. Receive DMA Main Operational Areas................................................................................... 77
Table 9-C. Receive Descriptor Address Storage ....................................................................................... 80
Table 9-D. Receive Free-Queue Read/Write Pointer Absolute Address Calculation................................ 83
Table 9-E. Receive Free-Queue Internal Address Storage ........................................................................ 83
Table 9-F. Receive Done-Queue Internal Address Storage ....................................................................... 88
Table 9-G. Transmit DMA Main Operational Areas ................................................................................. 97
Table 9-H. Done-Queue Error-Status Conditions.................................................................................... 103
Table 9-I. Transmit Descriptor Address Storage ..................................................................................... 105
Table 9-J. Transmit Pending-Queue Internal Address Storage................................................................ 108
Table 9-K. Transmit Done-Queue Internal Address Storage................................................................... 112
Table 11-A. Local Bus Signals (LBPXS Floating or Connected High) .................................................. 138
Table 11-B. Local Bus 8-Bit Width Address, LBHE Setting .................................................................. 141
Table 11-C. Local Bus 16-Bit Width Address, LD, LBHE Setting ......................................................... 142
Table 12-A. Instruction Codes ................................................................................................................. 159