Rainbow Electronics DS3131 - Manual (Page 25)

DS3131
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updated on the rising edge of PCLK. When the device is a target, this signal is an input and is sampled on the
rising edge of PCLK. When the device is not involved in a bus transaction, PFRAME is three-stated.
Signal Name:
PIRDY PIRDY PIRDY PIRDY
Signal Description:
PCI Initiator Ready
Signal Type:
Input/Output (three-state capable)
The initiator creates this active-low signal to signal the target that it is ready to send/accept or to continue
sending/accepting data. This signal handshakes with the PTRDY signal during a bus transaction to control the rate
at which data transfers across the bus. During a bus transaction, PIRDY is deasserted when the initiator cannot
temporarily accept or send data, and a wait state is invoked. When the device is an initiator, this signal is an output
and is updated on the rising edge of PCLK. When the device is a target, this signal is an input and is sampled on
the rising edge of PCLK. When the device is not involved in a bus transaction, PIRDY is three-stated.
Signal Name:
PTRDY PTRDY PTRDY PTRDY
Signal Description:
PCI Target Ready
Signal Type:
Input/Output (three-state capable)
The target creates this active-low signal to signal the initiator that it is ready to send/accept or to continue
sending/accepting data. This signal handshakes with the PIRDY signal during a bus transaction to control the rate
at which data transfers across the bus. During a bus transaction, PTRDY is deasserted when the target cannot
temporarily accept or send data, and a wait state is invoked. When the device is a target, this signal is an output
and is updated on the rising edge of PCLK. When the device is an initiator, this signal is an input and is sampled
on the rising edge of PCLK. When the device is not involved in a bus transaction, PTRDY is three-stated.
Signal Name:
PSTOP PSTOP PSTOP PSTOP
Signal Description:
PCI Stop
Signal Type:
Input/Output (three-state capable)
The target creates this active-low signal to signal the initiator to stop the current bus transaction. When the device
is a target, this signal is an output and is updated on the rising edge of PCLK. When the device is an initiator, this
signal is an input and is sampled on the rising edge of PCLK. When the device is not involved in a bus transaction,
PSTOP is three-stated.
Signal Name: PIDSEL
Signal Description: PCI Initialization Device Select
Signal Type:
Input
This input signal is used as a chip select during configuration read and write transactions. This signal is disabled
when the local bus is set in configuration mode (LMS = 1). When PIDSEL is set high during the address phase
of a bus transaction and the bus command signals (PCBE0 to PCBE3) indicate a register read or write, the device
allows access to the PCI configuration registers, and the PDEVSEL signal is asserted during the PCLK cycle.
PIDSEL is sampled on the rising edge of PCLK.
Signal Name:
PDEVSEL PDEVSEL PDEVSEL PDEVSEL
Signal Description:
PCI Device Select
Signal Type: Input/Output (three-state capable)
The target creates this active-low signal when it has decoded the address sent to it by the initiator as its own to
indicate that the address is valid. If the device is an initiator and does not see this signal asserted within six PCLK
cycles, the bus transaction is aborted and the PCI host is alerted. When the device is a target, this signal is an
output and is updated on the rising edge of PCLK. When the device is an initiator, this signal is an input and is
sampled on the rising edge of PCLK. When the device is not involved in a bus transaction, PDEVSEL is three-
stated.