Rainbow Electronics DS3131 - Manual (Page 43)

DS3131
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Bit 3/Status Bit for Receive HDLC Abort Detected (RABRT). This status bit is set to 1 if any of the receive
HDLC channels detects an abort. The RABRT bit is cleared when read and is not set again until another abort has
been detected. If enabled through the RABRT bit in the interrupt mask for SDMA (ISDMA), the setting of this bit
causes a hardware interrupt at the PCI bus through the PINTA signal pin and also at the LINT if the local bus is in
configuration mode.
Bit 4/Status Bit for Receive HDLC Length Check (RLENC). This status bit is set to 1 if any of the HDLC
channels:
• = exceeds the octet length count (if so enabled to check for octet length)
• = receives an HDLC packet that does not meet the minimum length criteria
• = experiences a nonintegral number of octets in between opening and closing flags
The RLENC bit is cleared when read and is not set again until another length violation has occurred. If enabled
through the RLENC bit in the interrupt mask for SDMA (ISDMA), the setting of this bit causes a hardware
interrupt at the PCI bus through the PINTA signal pin and also at the LINT if the local bus is in configuration
mode.
Bit 5/Status Bit for Receive FIFO Overflow (ROVFL). This status bit is set to 1 if any of the HDLC channels
experiences an overflow in the receive FIFO. The ROVFL bit is cleared when read and is not set again until
another overflow has occurred. If enabled through the ROVFL bit in the interrupt mask for SDMA (ISDMA), the
setting of this bit causes a hardware interrupt at the PCI bus through the PINTA signal pin and also at the LINT if
the local bus is in configuration mode.
Bit 6/Status Bit for Receive DMA Large Buffer Read (RLBR). This status bit is set to 1 each time the receive
DMA completes a single read or a burst read of the large buffer free queue. The RLBR bit is cleared when read
and is not be set again, until another read of the large buffer free queue has occurred. If enabled through the RLBR
bit in the interrupt mask for SDMA (ISDMA), the setting of this bit causes a hardware interrupt
at the PCI bus
through the PINTA signal pin and also at the LINT if the local bus is in configuration mode.
Bit 7/Status Bit for Receive DMA Large Buffer Read Error (RLBRE). This status bit is set to 1 each time the
receive DMA tries to read the large buffer free queue and it is empty. The RLBRE bit is cleared when read and is
not set again, until another read of the large buffer free queue detects that it is empty. If enabled through the
RLBRE bit in the interrupt mask for SDMA (ISDMA), the setting of this bit causes a hardware interrupt at the PCI
bus through the PINTA signal pin and also at the LINT if the local bus is in configuration mode.
Bit 8/Status Bit for Receive DMA Small Buffer Read (RSBR). This status bit is set to 1 each time the receive
DMA completes a single read or a burst read of the small buffer free queue. The RSBR bit is cleared when read
and is not set again, until another read of the small buffer free queue has occurred. If enabled through the RSBR
bit in the interrupt mask for SDMA (ISDMA), the setting of this bit causes a hardware interrupt at the PCI bus
through the PINTA signal pin and also at the LINT if the local bus is in configuration mode.
Bit 9/Status Bit for Receive DMA Small Buffer Read Error (RSBRE). This status bit is set to 1 each time the
receive DMA tries to read the small buffer free queue and it is empty. The RSBRE bit is cleared when read and is
not set again, until another read of the small buffer free queue detects that it is empty. If enabled through the
RSBRE bit in the interrupt mask for SDMA (ISDMA), the setting of this bit causes a hardware interrupt at the PCI
bus through the PINTA signal pin and also at the LINT if the local bus is in configuration mode.
Bit 10/Status Bit for Receive DMA Done-Queue Write (RDQW). This status bit is set to 1 when the receive
DMA writes to the done queue. Based of the setting of the receive done-queue threshold setting (RDQT0 to
RDQT2) bits in the receive DMA queues-control (RDMAQ) register, this bit is set either after each write or after a
programmable number of writes from 2 to 128 (Section
9.2.4 ). The RDQW bit is cleared when read and is not set
again until another write to the done queue has occurred. If enabled through the RDQW bit in the interrupt mask