Rainbow Electronics DS3131 - Manual (Page 114)

DS3131
114 of 174
Done-Queue FIFO Flush Timer
To ensure the done-queue FIFO gets flushed to the done queue on a regular basis, the transmit done-
queue FIFO flush timer (TDQFFT) is used by the DMA to determine the maximum wait time in between
writes. The TDQFFT is a 16-bit programmable counter that is decremented every PCLK divided by 256.
It is only monitored by the DMA when the transmit done-queue FIFO is enabled (TDQFE = 1). For a
33MHz PCLK, the timer is decremented every 7.76
µ
s. Each time the DMA writes to the done queue it
resets the timer to the count placed into it by the host. On initialization, the host sets a value into the
TDQFFT that indicates the maximum time the DMA should wait in between writes to the done queue.
For example, with a PCLK of 33MHz, the range of wait times is from 7.8
µ
s (RDQFFT = 0001h) to
508ms (RDQFFT = FFFFh).
Register Name: TDQFFT
Register Description: Transmit Done-Queue FIFO Flush Timer
Register Address:
0844h
Bit
# 7 6 5 4 3 2 1 0
Name TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0
Default 0 0 0 0 0 0 0 0
Bit # 15 14 13 12 11 10 9 8
Name TC15 TC14 TC13 TC12 TC11 TC10 TC9 TC8
Default 0 0 0 0 0 0 0 0
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 15/Transmit Done-Queue FIFO Flush Timer Control Bits (TC0 to TC15). Please note that on system
reset, the timer is set to 0000h, which is defined as an illegal setting. If the receive done-queue FIFO is to be
activated (TDQFE = 1), the host must first configure the timer to a proper state and then set the TDQFE bit
to 1.
0000h = illegal setting
0001h = timer count resets to 1
FFFFh = timer count resets to 65,536