Rainbow Electronics DS3131 - Manual (Page 13)

DS3131
13 of 174
Table 2-B. Initialization Steps
INITIALIZATION STEP COMMENTS
1) System Reset System reset can be invoked by either hardware action
through the PRST signal (recommended) or software
action through the RST control bit in the master reset and
ID register. All configuration registers are set to 0 (0000h)
by system reset.
2) Configure LBBMC Register Please note that this register is not affected by the
software-invoked system reset. It is forced to all zeros only
by the hardware reset.
3) Configure PCI This is achieved by asserting the PIDSEL signal.
4) Disable Transmit and Receive DMA for each
Channel Ensure the DMA is off on both the transmit and receive
sides through the channel-enable bit in the transmit and
receive RAM.
5) Configure Receive DMA Program the receive DMA configuration RAM.
6) Configure Receive FIFO Program the receive FIFO registers.
7) Configure Receive Layer 1 Program the receive port registers (RP[n]CR).
8) Configure Transmit DMA Program the transmit DMA configuration RAM.
9) Configure Transmit FIFO Program the transmit FIFO registers.
10) Configure Transmit Layer 2 Program the transmit HDLC port control registers
(TH[n]CR).
11) Configure Transmit Layer 1 Program the transmit port registers (TP[n]CR).
12) Configure Receive Layer 2 Program the receive HDLC port control registers
(RH[n]CR).
13) Enable Receive DMA for Each Channel Set the channel-enable bit in the receive DMA
configuration RAM for the channels in use.
14) Enable Transmit DMA for Each Channel Set the channel-enable bit in the transmit DMA
configuration RAM for the channels in use.
15) Configure Interrupts Optional,
16) Configure Master Control Register Set the RDE and TDE control bits in the master
configuration (MC) register.
Table 2-C. Indirect Registers
REGISTER NAME NUMBER OF INDIRECT REGISTERS
Receive DMA Configuration RDMAC 120 (three for each HDLC Channel)
1
Transmit DMA Configuration TDMAC 240 (six for each HDLC Channel) 1
Receive FIFO Starting Block Pointer RFSBP 40 (one for each HDLC Channel)
Receive FIFO Block Pointer RFBP 512 (one for each FIFO Block)
Receive FIFO High Watermark RFHWM 40 (one for each HDLC Channel)
Transmit FIFO Starting Block Pointer TFSBP 40 (one for each HDLC Channel)
Transmit FIFO Block Pointer TFBP 512 (one for each FIFO Block)
Transmit FIFO Low Watermark TFLWM 40 (one for each HDLC Channel)
1 On device initialization, the host needs only to write to one of the receive and one of the transmit DMA registers. See Sections 9.2.5 and 9.3.5
for details.