Rainbow Electronics DS3131 - Manual (Page 67)

DS3131
67 of 174
8.1.1 Receive High Watermark
The high watermark tells the device how many blocks should be written into the receive FIFO by the
HDLC controllers before the DMA begins sending the data to the PCI bus, or rather, how full the FIFO
should get before it should be emptied by the DMA. When the DMA begins reading the data from the
FIFO, it reads all available data and tries to completely empty the FIFO even if one or more EOFs (end
of frames) are detected. For example, if four blocks were link-listed together and the host programmed
the high watermark to three blocks, then the DMA would read the data out of the FIFO and transfer it to
the PCI bus after the HDLC controller had written three complete blocks in succession into the FIFO and
still had one block left to fill. The DMA would not read the data out of the FIFO again until another three
complete blocks had been written into the FIFO in succession by the HDLC controller or until an EOF
was detected. In this example of four blocks being link-listed together, the high watermark could also be
set to 1 or 2, but no other values would be allowed; the maximum value of the high watermark is the size
of the FIFO - 2. If an incoming packet does not fill the FIFO enough to reach the high watermark before
an EOF is detected, the DMA still requests that the data be sent to the PCI bus; it does not wait for
additional data to be written into the FIFO by the HDLC controllers.
8.1.2 Transmit Low Watermark
The low watermark tells the device how many blocks should be left in the FIFO before the DMA should
begin getting more data from the PCI bus, or rather, how empty the FIFO should get before it should be
filled again by the DMA. When the DMA begins reading the data from the PCI bus, it reads all available
data and tries to completely fill the FIFO even if one or more EOFs (HDLC packets) are detected. For
example, if five blocks were link-listed together and the host programmed the low watermark to two
blocks, then the DMA would read the data from the PCI bus and transfer it to the FIFO after the HDLC
controller has read three complete blocks in succession from the FIFO and, therefore, still had two
blocks left before the FIFO was empty. The DMA would not read the data from the PCI bus again until
another three complete blocks had been read from the FIFO in succession by the HDLC controllers. In
this example of five blocks being link-listed together, the low watermark could also be set to any value
from 1 to 4 (inclusive) but no other values would be allowed. When a new packet is written into a
completely empty FIFO by the DMA, the HDLC controllers wait until the FIFO fills beyond the low
watermark or until an EOF is seen before reading the data out of the FIFO.