Rainbow Electronics DS3131 User Manual
Page 110
DS3131
110 of 174
Register Name:
TDMAQ
Register Description:
Transmit DMA Queues Control
Register Address:
0880h
Bit
# 7 6 5 4 3 2 1 0
Name
reserved reserved reserved reserved TDQF TDQFE TPQF TPQFE
Default
0 0 0 0 0 0 0 0
Bit
# 15 14 13 12 11 10 9 8
Name
reserved reserved reserved reserved reserved TDQT2 TDQT1 TDQT0
Default
0 0 0 0 0 0 0 0
Note:
Bits that are underlined are read-only; all other bits are read-write.
Bit 0/Transmit Pending-Queue FIFO Enable (TPQFE). This bit must be set to 1 to enable the DMA to burst
read descriptors from the pending queue. If this bit is set to 0, descriptors are read one at a time.
0 = pending-queue burst read disabled
1 = pending-queue burst read enabled
Bit 1/Transmit Pending-Queue FIFO Flush (TPQF). When this bit is set to 1, the internal pending-queue FIFO
is flushed (currently loaded pending-queue descriptors are lost). This bit must be set to 0 for proper operation.
0 = FIFO in normal operation
1 = FIFO is flushed
Bit 2/Transmit Done-Queue FIFO Enable (TDQFE). See Section
9.3.4
for details.
Bit 3/Transmit Done-Queue FIFO Flush (TDQF). See Section
9.3.4
for details.
Bits 8 to 10/Transmit Done-Queue Status Bit Threshold Setting (TDQT0 to TDQT2). See Section
9.3.4
for
more details.