Rainbow Electronics DS3131 - Manual (Page 21)

DS3131
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Signal Name:
LBPXS
Signal Description:
Local Bus or Port Extension Select
Signal Type:
Input (with internal 10kΩ pullup)
This signal must be left open-circuited (or connected high) to activate and enable the local bus. When this signal is
connected low, the local bus is disabled and its signals are redefined to support 12 bit-synchronous HDLC
controllers on ports 28 to 39 (
Table 3-A ).
0 = local bus disabled
1 (or open -ircuited) = local bus enabled
Signal Name:
LD0 to LD15
Signal Description: Local Bus Nonmultiplexed Data Bus
Signal Type:
Input/Output (three-state capable)
In PCI bridge mode (LMS = 0), data from/to the PCI bus can be transferred to/from these signals. When writing
data to the local bus, these signals are outputs and updated on the rising edge of LCLK. When reading data from
the local bus, these signals are inputs, which are sampled on the rising edge of LCLK. Depending on the assertion
of the PCI byte enables (PCBE0 to PCBE3) and the local bus-width (LBW) control bit in the local bus bridge
mode control register (LBBMC), this data bus uses all 16 bits (LD[15:0]) or just the lower 8 bits (LD[7:0]) or the
upper 8 bits (LD[15:8]). If the upper LD bits (LD[15:8]) are used, then the local bus high-enable signal (LBHE) is
asserted during the bus transaction. If the local bus is not currently involved in a bus transaction, all 16 signals are
three-stated. When reading data from the local bus, these signals are outputs that are updated on the rising edge of
LCLK. When writing data to the local bus, these signals become inputs, which are sampled on the rising edge of
LCLK. In configuration mode (LMS = 1), the external host configures the device and obtains real-time status
information about the device through these signals. Only the 16-bit bus width is allowed (i.e., byte addressing is
not available).
Signal Name:
LA0 to LA19
Signal Description:
Local Bus Nonmultiplexed Address Bus
Signal Type: Input/Output (three-state capable)
In the PCI bridge mode (LMS = 0), these signals are outputs that are asserted on the rising edge of LCLK to
indicate which address is written to or read from. If bus arbitration is enabled through the local bus arbitration
(LARBE) control bit in the LBBMC register, these signals are three-stated when the local bus is not currently
involved in a bus transaction and driven when a bus transaction is active. When bus arbitration is disabled, these
signals are always driven. These signals are sampled on the rising edge of LCLK to determine the internal device
configuration register that the external host wishes to access. In configuration mode (LMS = 1), these signals are
inputs and only the bottom 16 bits (LA[15:0]) are active; the upper four (LA[19:16]) are ignored and should be
connected low.
Signal Name:
LWR LWR LWR LWR (LR/W W W W)
Signal Description:
Local Bus Write Enable (Local Bus Read/Write Select)
Signal Type:
Input/Output (three-state capable)
In the PCI bridge mode (LMS = 0), this output signal is asserted on the rising edge of LCLK. In Intel mode
(LIM = 0), it is asserted when data is to be written to the local bus. In Motorola mode (LIM = 1), this signal
determines whether a read or write is to occur. If bus arbitration is enabled through the LARBE control bit in the
LBBMC register, this signal is three-stated when the local bus is not currently involved in a bus transaction and
driven when a bus transaction is active. When bus arbitration is disabled, this signal is always driven. In
configuration mode (LMS = 1), this signal is sampled on the rising edge of LCLK. In Intel mode (LIM = 0), it
determines when data is to be written to the device. In Motorola mode (LIM = 1), this signal determines whether a
read or write is to occur.