Rainbow Electronics DS3131 - Manual (Page 38)

DS3131
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Bit 6/PCI Bus Orientation (PBO). This bit selects whether HDLC packet data on the PCI bus operates in either
Little Endian or Big Endian format. Little Endian byte ordering places the least significant byte at the lowest
address while Big Endian places the least significant byte at the highest address. This bit setting only affects
HDLC data on the PCI bus. All other PCI bus transactions to the internal device configuration registers, PCI
configuration registers, and local bus are always in Little Endian format.
0 = HDLC packet data on the PCI bus is in Little Endian format
1 = HDLC packet data on the PCI bus is in Big Endian format
Bits 7 to 12/BERT Port Select Bits 0 to 5 (BPS0 to BPS5). These six bits select which port has the dedicated
resources of the BERT.
000000 (00h) = Port 0
000001 (01h) = Port 1
000010 (02h) = Port 2
100110 (26h) = Port 38
100111 (27h) = Port 39
101000 (28h) = illegal setting
111111 (3Fh) = illegal setting
Bit 14/Transmit FIFO Priority Control Bit 0 (TFPC0); Bit 15/Transmit FIFO Priority Control Bit 1
(TFPC1). These two bits select the algorithm the FIFO uses to determine which HDLC channel gets the highest
priority to the DMA to transfer data from the PCI bus to the FIFO. In the priority-decoded scheme, the lower the
HDLC channel numbers, the higher the priority. See
Table 8-A .
00 = all HDLC channels are serviced round robin
01 = HDLC channels 1 and 2 are priority decoded; other HDLC channels are round robin
10 = HDLC channels 1 to 4 are priority decoded; other HDLC channels are round robin
11 = HDLC channels 1 to 16 are priority decoded; other HDLC channels are round robin