Rainbow Electronics DS3131 - Manual (Page 23)

DS3131
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Signal Name:
LBHE LBHE LBHE LBHE
Signal Description:
Local Bus Byte-High Enable (PCI Bridge Mode Only)
Signal Type: Output (three-state capable)
This active-low output signal is asserted when all 16 bits of the data bus (LD[15:0]) are active. It remains high if
only the lower 8 bits (LD[7:0)] are active. If bus arbitration is enabled through the LARBE control bit in the
LBBMC register, this signal is three-stated when the local bus is not currently involved in a bus transaction and
driven when a bus transaction is active. When bus arbitration is disabled, this signal is always driven. This signal
remains in three-state when the local bus is not involved in a bus transaction and is in configuration mode
(LMS = 1).
Signal Name:
LCLK
Signal Description: Local Bus Clock (PCI Bridge Mode Only)
Signal Type:
Output (three-state capable)
This signal outputs a buffered version of the clock applied at the PCLK input. All local bus signals are generated
and sampled from this clock. This output is three-stated when the local bus is in configuration mode (LMS = 1). It
can be disabled in the PCI bridge mode through the LBBMC register.
Signal Name:
LCS LCS LCS LCS
Signal Description:
Local Bus Chip Select (Configuration Mode Only)
Signal Type:
Input
This active-low signal must be asserted for the device to accept a read or write command from an external host.
This signal is ignored in the PCI bridge mode (LMS = 0) and should be connected high.
3.4 JTAG Signal Description
Signal Name: JTCLK
Signal Description:
JTAG IEEE 1149.1 Test Serial Clock
Signal Type:
Input
This signal is used to shift data into JTDI on the rising edge and out of JTDO on the falling edge. If not used, this
signal should be pulled high.
Signal Name: JTDI
Signal Description:
JTAG IEEE 1149.1 Test Serial-Data Input
Signal Type:
Input (with internal 10kΩ pullup)
Test instructions and data are clocked into this signal on the rising edge of JTCLK. If not used, this signal should
be pulled high. This signal has an internal pullup.
Signal Name:
JTDO
Signal Description:
JTAG IEEE 1149.1 Test Serial-Data Output
Signal Type: Output
Test instructions are clocked out of this signal on the falling edge of JTCLK. If not used, this signal should be left
open circuited.
Signal Name:
JTRST JTRST JTRST JTRST
Signal Description:
JTAG IEEE 1149.1 Test Reset
Signal Type:
Input (with internal 10kΩ pullup)
This signal is used to synchronously reset the test access port controller. At power-up, JTRST must be set low and
then high. This action sets the device into the boundary scan bypass mode, allowing normal device operation. If
boundary scan is not used, this signal should be held low. This signal has an internal pullup.
Signal Name:
JTMS
Signal Description:
JTAG IEEE 1149.1 Test Mode Select
Signal Type: Input (with internal 10kΩ pullup)
This signal is sampled on the rising edge of JTCLK and is used to place the test port into the various defined IEEE
1149.1 states. If not used, this signal should be pulled high. This signal has an internal pullup.