Rainbow Electronics DS3131 - Manual (Page 6)

DS3131
6 of 174
1. MAIN FEATURES
Layer 1
40 independent bit-synchronous physical ports
capable of speeds up to 52Mbps
Each port can be independently configured
Loopback in both directions (receive to transmit
and transmit to receive)
On-board BERT generation and detection
HDLC
40 independent full-duplex HDLC channels
132Mbps throughput in both the receive and
transmit directions with a 33MHz PCI clock
Transparent mode
Automatic flag detection and generation
Shared opening and closing flag
Interframe fill
Zero stuffing and destuffing
CRC16/32 checking and generation
Abort detection and generation
CRC error and long/short frame-error detection
Bit flip
Invert data
FIFO
Large 8kB receive and 8kB transmit buffers
maximize PCI bus efficiency
Small block size of 16 Bytes allows maximum
flexibility
Programmable low and high watermarks
Programmable HDLC channel priority setting
DMA
Efficient scatter-gather DMA minimizes PCI bus
accesses (same as the DS3134 Chateau)
Programmable small and large buffer sizes up to
8191 Bytes and algorithm select
Descriptor bursting to conserve PCI bus
bandwidth
Programmable packet-storage address offset
Identical receive and transmit descriptors
minimize host processing in store-and-
forward
Automatic channel disabling and enabling on
transmit errors
Receive packets are timestamped
Transmit packet priority setting
PCI Bus
32-bit, 33MHz
Version 2.1 Compliant; See t5 in the PCI Bus
AC Characteristics for a 1ns exception.
Note: This does not affect real-world
designs. DS3131 V
IH
is also slightly higher
than the PCI specification, as detailed in the
first page of Section
13 .
Contains extension signals that allow adoption to
custom buses
Can burst up to 256 32-bit words to maximize
bus efficiency
Local Bus
Can operate as a bridge from the PCI bus or a
configuration bus
Can arbitrate for the bus when in bridge mode
8 or 16 bits wide
Supports a 1MB address space when in bridge
mode
Supports Intel and Motorola bus timing
JTAG Test Access
3.3V low-power CMOS with 5V tolerant I/Os
272-pin plastic BGA package (27mm x 27mm)
Governing Specifications
The DS3131 fully meets the following specifications:
• = ANSI (American National Standards Institute) T1.403-1995 Network-to-Customer Installation DS1 Metallic
Interface March 21, 1995
• = PCI Local Bus Specification V2.1 June 1, 1995
• = ITU Q.921 March 1993
• =
ISO Standard 3309-1979 Data Communications–HDLC Procedures–Frame Structure