Rainbow Electronics DS3131 - Manual (Page 8)

DS3131
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The FIFO transfers data from the HDLC engines into the FIFO and checks to see if the FIFO has filled to
beyond the programmable high watermark. If it has, the FIFO signals to the DMA that data is ready to be
burst read from the FIFO to the PCI bus. The FIFO block controls the DMA block and it tells the DMA
when to transfer data from the FIFO to the PCI bus. Since the DS3131 can handle multiple HDLC
channels, it is possible that at any one time, several HDLC channels may need to have data transferred
from the FIFO to the PCI bus. The FIFO determines which HDLC channel the DMA handles next
through a host configurable algorithm, which allows the selection to be either round robin or priority,
decoded (with HDLC channel 1 getting the highest priority). Depending on the application, the selection
of this algorithm can be quite important. The DS3131 cannot control when it is granted PCI bus access
and, if bus access is restricted, then the host may wish to prioritize which HDLC channels get top
priority access to the PCI bus when it is granted to the DS3131.
When the DMA transfers data from the FIFO to the PCI bus, it burst reads all available data in the FIFO
(even if the FIFO contains multiple HDLC packets) and tries to empty the FIFO. If an incoming HDLC
packet is not large enough to fill the FIFO to the high watermark, then the FIFO does not wait for more
data to enter. It signals the DMA that an end-of-frame (EOF) was detected and that data is ready to be
transferred from the FIFO to the PCI bus.
In the transmit path, a very similar process occurs. As soon as an HDLC channel is enabled, the HDLC
(Layer 2) engines begin requesting data from the FIFO. Like the receive side, the 40 ports are priority
decoded with port 0 (HDLC channel #1) getting the highest priority. Therefore, if multiple ports are
requesting packet data, the FIFO first satisfies the requirements on all the enabled HDLC channels in the
lower numbered ports before moving to the higher numbered ports. Again, there is no potential data loss
as long as the transmit throughput maximum of 132Mbps is not exceeded. When the FIFO detects that an
HDLC engine needs data, it then transfers the data from the FIFO to the HDLC engines. If the FIFO
detects it is below the low watermark, it checks with the DMA to see if there is any data available for
that HDLC channel. The DMA knows if any data is available because the host on the PCI bus has
informed it of such through the pending-queue descriptor. When the DMA detects that data is available,
it informs the FIFO, which then decides which HDLC channel gets the highest priority to the DMA to
transfer data from the PCI bus into the FIFO. Again, since the DS3131 can handle multiple HDLC
channels, it is possible that at any one time, several HDLC channels may need the DMA to burst data
from the PCI bus into the FIFO. The FIFO determines which HDLC channel the DMA handles next
through a host-configurable algorithm, which allows the selection to be either round robin or priority
decoded (with HDLC channel 1 getting the highest priority).
When the DMA begins burst-writing data into the FIFO, it tries to completely fill the FIFO with HDLC
packet data even if it that means writing multiple packets. Once the FIFO detects that the DMA has filled
it to beyond the low watermark (or an EOF is reached), the FIFO begins transferring data to the HDLC
controller.
One of the DS3131’s unique attributes is the DMA’s structure. The DMA maintains maximum
flexibility, yet reduces the number of bus cycles required to transfer packet data. The DMA uses a
flexible scatter/gather technique, which allows that packet data to be placed anywhere within the 32-bit
address space. The user has the option on the receive side of two different buffer sizes, which are called
“large” and “small” but that can be set to any size up to 8191 Bytes. The user can choose to store the
incoming data in the large buffers, in the small buffers, or in the small buffers first, filling the large
buffers as needed. The varying buffer storage options allow the user to make the best use of available
memory and balance the trade-off between latency and bus utilization.