Rainbow Electronics DS3131 - Manual (Page 33)

DS3131
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4.7 BERT Registers (5xx)
OFFSET/
ADDRESS
NAME REGISTER SECTION
0500 BERTC0 BERT Control 0 6.4
0504 BERTC1 BERT Control 1 6.4
0508 BERTRP0 BERT Repetitive Pattern Set 0 (lower word) 6.4
050C BERTRP1 BERT Repetitive Pattern Set 1 (upper word) 6.4
0510 BERTBC0 BERT Bit Counter 0 (lower word) 6.4
0514 BERTBC1 BERT Bit Counter 1 (upper word) 6.4
0518 BERTEC0 BERT Error Counter 0 (lower word) 6.4
051C BERTEC1 BERT Error Counter 1 (upper word) 6.4
4.8 Receive DMA Registers (7xx)
OFFSET/
ADDRESS
NAME REGISTER SECTION
0700 RFQBA0 Receive Free-Queue Base Address 0 (lower word) 9.2.3
0704 RFQBA1 Receive Free-Queue Base Address 1 (upper word) 9.2.3
0708 RFQEA Receive Free-Queue End Address 9.2.3
070C RFQSBSA Receive Free-Queue Small Buffer Start Address 9.2.3
0710 RFQLBWP Receive Free-Queue Large Buffer Host Write Pointer 9.2.3
0714 RFQSBWP Receive Free-Queue Small Buffer Host Write Pointer 9.2.3
0718 RFQLBRP Receive Free-Queue Large Buffer DMA Read Pointer 9.2.3
071C RFQSBRP Receive Free-Queue Small Buffer DMA Read Pointer 9.2.3
0730 RDQBA0 Receive Done-Queue Base Address 0 (lower word) 9.2.4
0734 RDQBA1 Receive Done-Queue Base Address 1 (upper word) 9.2.4
0738 RDQEA Receive Done-Queue End Address 9.2.4
073C RDQRP Receive Done-Queue Host Read Pointer 9.2.4
0740 RDQWP Receive Done-Queue DMA Write Pointer 9.2.4
0744 RDQFFT Receive Done-Queue FIFO Flush Timer 9.2.4
0750 RDBA0 Receive Descriptor Base Address 0 (lower word) 9.2.2
0754 RDBA1 Receive Descriptor Base Address 1 (upper word) 9.2.2
0770 RDMACIS Receive DMA Configuration Indirect Select 9.3.5
0774 RDMAC Receive DMA Configuration 9.3.5
0780 RDMAQ Receive DMA Queues Control 9.2.3/9.2.4
0790 RLBS Receive Large Buffer Size 9.2.1
0794 RSBS Receive Small Buffer Size 9.2.1