Rainbow Electronics DS3131 User Manual

Page 22

DS3131

22 of 174

Signal Name:

LRD

LRD (LDS

LDS

LDS)

Signal Description:

Local Bus Read Enable (Local Bus Data Strobe)

Signal Type:

Input/Output (three-state capable)

In the PCI bridge mode (LMS = 0), this active-low output signal is asserted on the rising edge of LCLK. In Intel
mode (LIM = 0), it is asserted when data is to be read from the local bus. In Motorola mode (LIM = 1), the rising
edge is used to write data into the slave device. If bus arbitration is enabled through the LARBE control bit in the
LBBMC register, this signal is three-stated when the local bus is not currently involved in a bus transaction and
driven when a bus transaction is active. When bus arbitration is disabled, this signal is always driven. In
configuration mode (LMS = 1), this signal is an active-low input that is sampled on the rising edge of LCLK. In
Intel mode (LIM = 0), it determines when data is to be read from the device. In Motorola mode (LIM = 1), the
rising edge writes data into the device.

Signal Name:

LINT

Signal Description:

Local Bus Interrupt

Signal Type:

Input/Output (open drain)

In the PCI bridge mode (LMS = 0), this active-low signal is an input that is sampled on the rising edge of LCLK.
If asserted and unmasked, this signal causes an interrupt at the PCI bus through the PINTA signal. If not used in
PCI bridge mode, this signal should be connected high. In configuration mode (LMS = 1), this signal is an open-
drain output that is forced low if one or more unmasked interrupt sources within the device is active. The signal
remains low until either the interrupt is serviced or masked.

Signal Name:

LRDY

Signal Description:

Local Bus PCI Bridge Ready (PCI Bridge Mode Only)

Signal Type:

Input

This active-low signal is sampled on the rising edge of LCLK to determine when a bus transaction is complete.
This signal is only examined when a bus transaction is taking place. This signal is ignored when the local bus is in
configuration mode (LMS = 1) and should be connected high.

Signal Name:

LHLDA (LBG

LBG

LBG)

Signal Description:

Local Bus Hold Acknowledge (Local Bus Grant) (PCI Bridge Mode Only)

Signal Type:

Input

This input signal is sampled on the rising edge of LCLK to determine when the device has been granted access to
the bus. In Intel mode (LIM = 0), this is an active-high signal; in Motorola mode (LIM = 1) this is an active-low
signal. This signal is ignored and should be connected high when the local bus is in configuration mode
(LMS = 1). Also, in PCI bridge mode (LMS = 0), this signal should be wired deasserted when the local bus
arbitration is disabled through the LBBMC register.

Signal Name:

LHOLD (LBR

LBR

LBR)

Signal Description:

Local Bus Hold (Local Bus Request) (PCI Bridge Mode Only)

Signal Type:

Output

This signal is asserted when the DS3131 is attempting to control the local bus. In Intel mode (LIM = 0), this signal
is an active-high signal; in Motorola mode (LIM = 1) this signal is an active-low signal. It is deasserted
concurrently with LBGACK. This signal is three-stated when the local bus is in configuration mode (LMS = 1)
and also in PCI bridge mode (LMS = 0) when the local bus arbitration is disabled through the LBBMC register.

Signal Name:

LBGACK

Signal Description:

Local Bus Grant Acknowledge (PCI Bridge Mode Only)

Signal Type:

Output (three-state capable)

This active-low signal is asserted when the local bus hold-acknowledge/bus grant signal (LHLDA/LBG) has been
detected and continues its assertion for a programmable (32 to 1,048,576) number of LCLKs, based on the local
bus arbitration timer setting in the LBBMC register. This signal is three-stated when the local bus is in
configuration mode (LMS = 1).