Rainbow Electronics DS3131 - Manual (Page 26)

DS3131
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Signal Name:
PREQ PREQ PREQ PREQ
Signal Description:
PCI Bus Request
Signal Type: Output (three-state capable)
The initiator asserts this active-low signal to request that the PCI bus arbiter allow it access to the bus. PREQ is
updated on the rising edge of PCLK.
Signal Name:
PGNT PGNT PGNT PGNT
Signal Description: PCI Bus Grant
Signal Type:
Input
The PCI bus arbiter asserts this active-low signal to indicate to the PCI requesting agent that access to the PCI bus
has been granted. The device samples PGNT on the rising edge of PCLK and, if detected, initiates a bus
transaction when it has sensed that the PFRAME signal has been deasserted.
Signal Name:
PPERR PPERR PPERR PPERR
Signal Description:
PCI Parity Error
Signal Type:
Input/Output (three-state capable)
This active-low signal reports parity errors. PPERR can be enabled and disabled through the PCI configuration
registers. This signal is updated on the rising edge of PCLK.
Signal Name:
PSERR PSERR PSERR PSERR
Signal Description: PCI System Error
Signal Type: Output (open drain)
This active-low signal reports any parity errors that occur during the address phase. PSERR can be enabled and
disabled through the PCI configuration registers. This signal is updated on the rising edge of PCLK.
Signal Name:
PINTA PINTA PINTA PINTA
Signal Description:
PCI Interrupt
Signal Type:
Output (open drain)
This active-low (open drain) signal is asserted low asynchronously when the device is requesting attention from
the device driver. PINTA is deasserted when the device-interrupting source has been serviced or masked. This
signal is updated on the rising edge of PCLK.
3.6 PCI Extension Signals
These signals are not part of the normal PCI bus signal set. There are additional signals that are asserted when the
BoSS is an initiator on the PCI bus to help users interpret the normal PCI bus signal set and connect them to a non-
PCI environment like an Intel i960-type bus.
Signal Name:
PXAS PXAS PXAS PXAS
Signal Description: PCI Extension Address Strobe
Signal Type:
Output
This active-low signal is asserted low on the same clock edge as PFRAME and is deasserted after one clock
period. This signal is only asserted when the device is an initiator. This signal is an output and is updated on the
rising edge of PCLK.
Signal Name:
PXDS PXDS PXDS PXDS
Signal Description: PCI Extension Data Strobe
Signal Type: Output
This active-low signal is asserted when the PCI bus either contains valid data to be read from the device or can
accept valid data that is written into the device. This signal is only asserted when the device is an initiator. This
signal is an output and is updated on the rising edge of PCLK.