Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 744)

Mentor VIP AE AXI3/4 User Guide, V10.2b 724
SystemVerilog AXI3 and AXI4 Test Programs
SystemVerilog AXI4 Slave BFM Test Program
September 2013
// burst or phase level depending upon slave working mode.
task automatic handle_read(input axi4_transaction read_trans);
addr_t addr[];
bit [7:0] mem_data[];
set_read_data_valid_delay(read_trans);
for(int i = 0; bfm.get_read_addr(read_trans, i, addr); i++)
begin
mem_data = new[addr.size()];
for (int j = 0; j < addr.size(); j++)
mem_data[j] = do_byte_read(addr[j]);
bfm.set_read_data(read_trans, i, addr, mem_data);
if (slave_mode == AXI4_PHASE_SLAVE)
bfm.execute_read_data_phase(read_trans, i);
end
if (slave_mode == AXI4_TRANSACTION_SLAVE)
bfm.execute_read_data_burst(read_trans);
endtask
// Task : process_write
// This method keep receiving write address phase and calls
// another method to
// process received transaction.
task process_write;
forever
begin
axi4_transaction write_trans;
write_trans = bfm.create_slave_transaction();
bfm.get_write_addr_phase(write_trans);
fork
begin
automatic axi4_transaction t = write_trans;
handle_write(t);
end
join_none
#0;
end
endtask