Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 222)

Mentor VIP AE AXI3/4 User Guide, V10.2b 204
VHDL AXI3 and AXI4 Master BFMs
Master BFM Protocol Support
September 2013
on page 630 “AXI4 Advanced Slave API Definition” on page 643 for more details on
the application of the path_id.
•
tr_if is a signal definition that passes the content of a transaction between the VHDL and
SystemVerilog environments.
Master BFM Protocol Support
The AXI3 master BFM supports the AMBA AXI3 protocol with restrictions detailed in
“Protocol Restrictions” on page 1. In addition to the standard protocol, it supports user sideband
signals AWUSER and ARUSER.
The AXI4 master BFM supports the AMBA AXI4 protocol with restrictions detailed in
“Protocol Restrictions” on page 1.
Master Timing and Events
For detailed timing diagrams of the protocol bus activity and details of the following master
BFM API timing and events, refer to the relevant AMBA AXI Protocol Specification chapter.
The AMBA AXI specification does not define any timescale or clock period with signal events
sampled and driven at rising ACLK edges. Therefore, the master BFM does not contain any
timescale, timeunit, or timeprecision declarations with the signal setup and hold times specified
in units of simulator time-steps.
Master BFM Configuration
The master BFM supports the full range of signals defined for the AMBA AXI protocol
specification. It has parameters you can use to configure the widths of the address, ID and data
signals, and transaction fields to configure timeout factors, slave exclusive support, setup and
hold times, etc.
The address, ID and data signal widths can be changed from their default settings by assigning
them with new values, usually performed in the top-level module of the testbench. These new
values are then passed into the master BFM via a parameter port list of the master BFM
component.
Table 8-1 lists the parameter names for the address, ID and data signals, and their default
values.
Table 8-1. Master BFM Signal Width Parameters
Signal Width Parameter Description
**_ADDRESS_WIDTH Address signal width in bits. This applies to the ARADDR and
AWADDR signals. Refer to the AMBA AXI Protocol
specification for more details. Default: 32.