Monitor assertions – Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM User Manual
Page 509
VHDL AXI3 and AXI4 Monitor BFMs
Monitor Assertions
Mentor VIP AE AXI3/4 User Guide, V10.2b
489
September 2013
1.
Refer to
for details of simulator time-steps.
Monitor Assertions
The monitor BFM performs protocol error checking via built-in assertions.
Note
The built-in BFM assertions are independent of programming language and simulator.
**_CONFIG_SLAVE_END_ADDR
Configures the end address map for
the slave.
**_CONFIG_READ_DATA_REORDERING_DEPTH
The slave read reordering depth. Refer
to the AMBA AXI Protocol specification
for more details. Default: 1.
Error Detection
**_CONFIG_ENABLE_ALL_ASSERTIONS
Global enable/disable of all assertion
checks in the BFM.
0 = disabled
1 = enabled (default)
**_CONFIG_ENABLE_ASSERTION
Individual enable/disable of assertion
check in the BFM.
0 = disabled
1 = enabled (default)
Table 10-2. Monitor BFM Configuration (cont.)
Configuration Field
Description
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)