Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 711)

Assertions
AXI4 Assertions
Mentor VIP AE AXI3/4 User Guide, V10.2b 691
September 2013
AXI4-
60174 AXI4_WRITE_DATA_BEFORE_
ADDRESS A write data beat has occurred
before the corresponding address
phase.
AXI4-
60175 AXI4_WRITE_DATA_UNKN_ON_INVALID_
LANE On a lane whose strobe is 0 WDATA
has an X value/WDATA has a Z
value.
AXI4-
60176 AXI4_WRITE_DATA_UNKN_ON_VALID_LANE On a lane whose strobe is 1 WDATA
has an X value/WDATA has a Z
value.
AXI4-
60177 AXI4_WRITE_EXCLUSIVE_ENCODING_
VIOLATION A write-only interface does not
support exclusive accesses. A10.2.3
AXI4-
60178 AXI4_WRITE_RESPONSE_WITHOUT_
ADDR_DATA An unexpected write response has
occurred (there are no outstanding
write transactions with this id).
AXI4-
60179 AXI4_WRITE_STROBE_FIXED_BURST_
VIOLATION Write strobe(s) incorrect for the
address/size of a fixed transfer.
AXI4-
60180 AXI4_WRITE_TRANSFER_EXCEEDS_
ADDRESS_SPACE This write transfer runs off the edge
of the address space defined by
AXI4_ADDRESS_WIDTH. A10.3.1
AXI4-
60181 AXI4_WRONG_ARREGION_FOR_SLAVE_
WITH_SINGLE_ADDRESS_
DECODE The region value should be 4'b0000
for a read from a slave with a single
address decode in the region map. A8.2.1
AXI4-
60182 AXI4_WRONG_AWREGION_FOR_SLAVE_
WITH_SINGLE_ADDRESS_
DECODE The region value should be 4'b0000
for a write to a slave with a single
address decode in the region map. A8.2.1
AXI4-
60183 AXI4_WSTRB_CHANGED_BEFORE_
WREADY The value of WSTRB has changed
from its initial value between the time
WVALID was asserted and before
WREADY was asserted. A3.2.1
AXI4-
60184 AXI4_WSTRB_UNKN WSTRB has an X value/WSTRB has
a Z value.
AXI4-
60185 AXI4_WUSER_CHANGED_BEFORE_
WREADY The value of WUSER has changed
from its initial value between the time
WVALID was asserted and before
WREADY was asserted. A3.2.1
AXI4-
60186 AXI4_WUSER_UNKN WUSER has an X value/WUSER has
a Z value.
AXI4-
60187 AXI4_WVALID_DEASSERTED_BEFORE_
WREADY WVALID has been de-asserted
before WREADY was asserted. A3.2.1
AXI4-
60188 AXI4_WVALID_HIGH_ON_FIRST_CLOCK A master interface must begin driving
WVALID high only at a rising clock
edge after ARESETn is HIGH. A3.1.2
AXI4-
60189 AXI4_WVALID_UNKN WVALID has an X value/WVALID
has a Z value.
Table A-2. AXI4 Assertions (cont.)
Error
Code Error Name Description Property
Ref