Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 47)

SystemVerilog API Overview
Operational Transaction Fields
Mentor VIP AE AXI3/4 User Guide, V10.2b 29
September 2013
AXI4 BFM *VALID Signal Delay Transaction Fields
The transaction record contains a *_valid_delay transaction field for each of the five protocol
channels to configure the delay value prior to the assertion of the *VALID signal for the
channel. The master BFM holds the delay configuration for the *VALID signals that it asserts,
and the slave BFM holds the delay configuration for the *VALID signals that it asserts.
Table 2-3 below specifies which *_valid_delay fields are configured by the master and slave
BFMs.
Table 2-3. Master and Slave*_valid_delay Configuration Fields
Note
In the transaction record, the data channel handshake signal transaction field
(data_valid_delay[]) is defined as an array, which allows you to configure the *VALID
delay on a per data phase (beat) basis in a transaction.
AXI4 BFM *READY Handshake Signal Delay Transaction Fields
The transaction record contains a *_ready_delay transaction field for each of the five protocol
channels to store the delay value that occurred between the assertion of the *VALID and
*READY handshake signals for the channel.
Table 2-4 specifies the *_ready_delay field
corresponding to the *READY signal delay.
Table 2-4. Master &Slave *_ready_delay Transaction Fields
Note
In the transaction record, the data channel handshake signal transaction field
(data_ready_delay[]) is defined as an array so that the *READY delay can be recorded on
a per data phase (beat) basis in a transaction.
Signal Operational Transaction Field Configuration BFM
AWVALID address_valid_delay Master
WVALID data_valid_delay Master
BVALID write_response_valid_delay Slave
ARVALID address_valid_delay Master
RVALID data_valid_delay Slave
Signal Operational Transaction Field
AWREADY address_ready_delay
WREADY data_ready_delay
BREADY write_response_ready_delay
ARREADY address_ready_delay
RREADY data_ready_delay