Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 188)

Mentor VIP AE AXI3/4 User Guide, V10.2b 170
SystemVerilog Tutorials
Verifying a Master DUT
September 2013
Example 6-35 shows the ARREADY signal delayed by 2 ACLK cycles. You can edit this
variable to change the ARREADY signal delay.
Example 6-35. m_rd_addr_phase_ready_delay
// Variable : m_rd_addr_phase_ready_delay
int m_rd_addr_phase_ready_delay = 2;
m_wr_addr_phase_ready_delay
The m_wr_addr_phase_ready_delay variable holds the AWREADY signal delay. The delay
value extends the length of the write address phase by a number of ACLK cycles. The starting
point of the delay is determined by the
slave_ready_delay_mode variable configuration.
Example 6-36 shows the AWREADY signal delayed by 2 ACLK cycles. You can edit this
variable to change the AWREADY signal delay.
Example 6-36. m_wr_addr_phase_ready_delay
// Variable : m_wr_addr_phase_ready_delay
int m_wr_addr_phase_ready_delay = 2;
m_wr_data_phase_ready_delay
The m_wr_data_phase_ready_delay variable holds the WREADY signal delay. The delay value
extends the length of each write data phase (beat) in a write data burst by a number of ACLK
cycles. The starting point of the delay is determined by the
slave_ready_delay_mode variable
configuration.
Example 6-37 shows the WREADY signal delayed by 2 ACLK cycles. You can edit this function
to change the WREADY signal delay.
Example 6-37. m_wr_data_phase_ready_delay
// Variable : m_wr_data_phase_ready_delay
int m_wr_data_phase_ready_delay = 2;
set_read_data_valid_delay()
The set_read_data_valid_delay() function, when called, configures the RVALID signal to be
delayed by a number of ACLK cycles with the effect of delaying the start of each read data
phase (beat) in a read data burst. The delay value of the RVALID signal, for each read data
phase, is stored in an array element of the data_valid_delay transaction field.