Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 176)

Mentor VIP AE AXI3/4 User Guide, V10.2b 158
SystemVerilog Tutorials
Verifying a Master DUT
September 2013
The set_read_address_ready_delay() function, when called, configures the ARREADY
handshake signal to be delayed by a number of ACLK cycles, which extends the length of the
read address phase. The starting point of the delay is determined by the delay_mode operational
transaction field (refer to
“AXI3 BFM Delay Mode” on page 30 for details). Example 6-20
demonstrates setting the ARREADY signal delay by 4 ACLK cycles.
You can edit this function to change the ARREADY signal delay.
Example 6-20. set_read_address_ready_delay()
// Function : set_read_address_ready_delay
// This is used to set read address phase ready delay
// to extend phase
function void set_read_address_ready_delay(axi_transaction trans);
trans.set_address_ready_delay(4);
endfunction
The set_write_address_ready_delay() function, when called, configures the AWREADY
handshake signal to be delayed by a number of ACLK cycles, which extends the length of the
write address phase. The starting point of the delay is determined by the delay_mode
operational transaction field (refer to
“AXI3 BFM Delay Mode” on page 30 for details).
Example 6-21 demonstrates setting the AWREADY signal delay by 2 ACLK cycles.
You can edit this function to change the AWREADY signal delay.
Example 6-21. set_write_address_ready_delay()
// Function : set_write_address_ready_delay
// This is used to set write address phase ready delay
// to extend phase
function void set_write_address_ready_delay(axi_transaction trans);
trans.set_address_ready_delay(2);
endfunction
The set_write_data_ready_delay() function, when called, configures the WREADY signal
handshake to be delayed by a number of ACLK cycles, which extends the length of each write
data phase (beat) in a write data burst. The starting point of the delay is determined by the
configuration of the delay_mode operational transaction field (refer to
“AXI3 BFM Delay
Mode” on page 30 for details).
For each write data phase (beat), the delay value of the WREADY signal is stored in an element
of the data_ready_delay[] array for the transaction, as demonstrated in
Example 6-22 .