Write burst transaction creation and execution, The code excerpt in, Example 11-3 – Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM User Manual
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Mentor VIP AE AXI3/4 User Guide, V10.2b
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VHDL Tutorials
Verifying a Slave DUT
September 2013
The read data is obtained using the
procedure to get the data_words[0]
transaction field value. The result of the read data is compared with the expected data—and a
report message displays the transcript.
Example 11-3. Read Transaction Creation and Execution
--Read data from address 1.
create_read_transaction(1, tr_id, index, axi_tr_if_0(index));
set_id(1, tr_id, index, axi_tr_if_0(index));
set_size(AXI_BYTES_1, tr_id, index, axi_tr_if_0(index));
execute_transaction(tr_id, index, axi_tr_if_0(index));
get_data_words(data_words, tr_id, index, axi_tr_if_0(index));
if(data_words(31 downto 0) = x"00000100") then
report "master_test_program: Read correct data (1) at address (1)";
else
hwrite(lp, data_words(31 downto 0));
report "master_test_program: Error: Expected data (1) at address 1,
but got " & lp.all;
end if;
In the complete Master Test Program, three subsequent read transactions are created and
executed in a similar manner to that shown in
code listing for details.
Write Burst Transaction Creation and Execution
The code excerpt in
write burst transaction by providing the start address and burst length arguments. The actual
length of the burst on the protocol signals is 7+1=8.
Note
The burst length argument passed to the
procedure is 1 less
than the number of transfers (beats) in the burst. This aligns the burst length argument
value with the value placed on the AWLEN protocol signals.
procedure is then called eight times to set the data_words field of the
write transaction for each beat of the data burst. For this write transaction, all data byte lanes
contain valid data on each beat of the data burst, therefore a ‘for loop’ calls the
procedure to set the write_strobes fields of the transaction to 15 for each
beat of the burst.
procedure configures the write burst transaction to allow the
write address phase and write data burst to start simultaneously
(AXI_DATA_WITH_ADDRESS) when executed. The write transaction is then executed onto
the protocol signals.