Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 693)

Assertions
AXI3 Assertions
Mentor VIP AE AXI3/4 User Guide, V10.2b 673
September 2013
Error
Code Error Name Description Property
Ref
AXI3-
60115 AXI_WDATA_CHANGED_BEFORE_
WREADY_ON_INVALID_LANE On a lane whose strobe is 0, the value of
WDATA has changed from its initial value
between the time WVALID was asserted, and
before WREADY was asserted. A3.2.1
AXI3-
60116 AXI_WDATA_CHANGED_BEFORE_
WREADY_ON_VALID_LANE On a lane whose strobe is 1, the value of
WDATA has changed from its initial value
between the time WVALID was asserted, and
before WREADY was asserted. A3.2.1
AXI3-
60117 AXI_WLAST_CHANGED_BEFORE_
WREADY The value of WLAST has changed from its
initial value between the time WVALID was
asserted, and before WREADY was
asserted. A3.2.1
AXI3-
60118 AXI_WID_CHANGED_BEFORE_
WREADY The value of WID has changed from its initial
value between the time WVALID was
asserted, and before WREADY was
asserted. A3.2.1
AXI3-
60119 AXI_WLAST_UNKN WLAST has an X or Z value. A2.3
AXI3-
60120 AXI_WID_UNKN WID has an X or Z value. A2.3
AXI3-
60121 AXI_WREADY_UNKN WREADY has an X or Z value. A2.3
AXI3-
60122 AXI_WRITE_ALLOCATE_WHEN_
NON_MODIFIABLE_12 The WA bit of the cache transaction field
should not be HIGH when the Modifiable bit
is LOW. A4.4
AXI3-
60123 AXI_WRITE_ALLOCATE_WHEN_
NON_MODIFIABLE_13 The WA of the cache transaction field bit
should not be HIGH when the Modifiable bit
is LOW. A4.4
AXI3-
60124 AXI_WRITE_ALLOCATE_WHEN_
NON_MODIFIABLE_4 The WA of the cache transaction field bit
should not be HIGH when the Modifiable bit
is LOW. A4.4
AXI3-
60125 AXI_WRITE_ALLOCATE_WHEN_
NON_MODIFIABLE_5 The WA of the cache transaction field bit
should not be HIGH when the Modifiable bit
is LOW. A4.4
AXI3-
60126 AXI_WRITE_ALLOCATE_WHEN_
NON_MODIFIABLE_8 The WA of the cache transaction field bit
should not be HIGH when the Modifiable bit
is LOW. A4.4
AXI3-
60127 AXI_WRITE_ALLOCATE_WHEN_
NON_MODIFIABLE_9 The WA of the cache transaction field bit
should not be HIGH when the Modifiable bit
is LOW. A4.4
AXI3-
60128 AXI_WRITE_BURST_SIZE_
VIOLATION In this write transaction, size has been set
greater than the defined data bus width. A3.4.1
AXI3-
60129 AXI_WRITE_DATA_BEFORE_
ADDRESS A write data beat has occurred before the
corresponding address phase. -
Table A-1. AXI3 Assertions (cont.)