Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 210)

Mentor VIP AE AXI3/4 User Guide, V10.2b 192
VHDL API Overview
Creating Transactions
September 2013
id A bit vector (of length equal to the ARID/AWID signal bus
width) to hold the identification tag of a transaction. The id
value is transferred over the AWID/BID signals for a write
transaction and over the ARID/RID signals for a read
transaction.
burst_length A 4-bit (8-bit for AXI4) vector to hold the burst length of a
transaction. The burst_length value is transferred over the
ARLEN or AWLEN signals for a read or write transaction,
respectively.
addr_user A bit vector (of length equal to the ARUSER/AWUSER signal
bus width) to hold the address channel user data of a
transaction. The addr_data value is transferred over the
ARUSER or AWUSER signals for a read or write transaction,
respectively.
data_words An unsized array of bit vectors (of length equal to the greater of
the RDATA/WDATA signal bus widths) to hold the data words
of the payload. A data_words array element is transferred over
the RDATA or WDATA signals per beat of the read or write
data channel, respectively.
write_strobes An unsized array of bit vectors (of length equal to the WDATA
signal bus width divided by 8) to hold the write strobes. A
write_strobes array element is transferred over the WSTRB
signals per beat of the write data channel.
resp An unsized enumeration array to hold the responses of a
transaction. The types of response are:
**_OKAY;
**_EXOKAY;
**_SLVERR;
**_DECERR;
A resp array element value is transferred over the RRESP
signals per beat of the read data channel, and over the BRESP
signals for a write transaction, respectively.
Operational Transaction Fields
read_or_write An enumeration to hold the read or write control flag. The types
of read_or_write are:
**_TRANS_READ
**_TRANS_WRITE
address_valid_delay An integer to hold the delay value of the address channel
AWVALID and ARVALID signals (measured in ACLK cycles)
for a read or write transaction, respectively.
data_valid_delay An unsized array of integers to hold the delay values of the
data channel WVALID and RVALID signals (measured in
ACLK cycles) for a read or write transaction, respectively.
write_response_valid_delay An integer to hold the delay value of the write response
channel BVALID signal (measured in ACLK cycles) for a write
transaction.
Table 7-1. Transaction Fields (cont.)
Transaction Field Description