Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 200)

Mentor VIP AE AXI3/4 User Guide, V10.2b 182
SystemVerilog Tutorials
Verifying a Master DUT
September 2013
write channel address phase to occur with a call to the blocking get_write_addr_cycle() task. A
received write address phase indicates that the AWVALID signal has been asserted, triggering
the starting point for the delay of the AWREADY signal by the number of ACLK cycles defined
by
m_wr_addr_phase_ready_delay . Another call to the execute_write_addr_ready() task to
assert the AWREADY signal completes the AWREADY handling. The seen_valid_ready flag is
set to indicate the end of a address phase when both AWVALID and AWREADY are asserted.
If the slave_delay_ready_mode = AXI4_TRANS2READY then a check of the seen_valid_ready
flag is performed to indicate that a previous write address phase has completed. If a write
address phase is still active (indicated by either AWVALID or AWREADY not asserted) then the
code waits until the previous write address phase has completed. The AWREADY signal is then
deasserted using the nonblocking call to the
execute_write_addr_ready() task and waits for the
number of ACLK cycles defined by m_wr_addr_phase_ready_delay . A nonblocking call to the
execute_write_addr_ready() task to assert the AWREADY signal completes the AWREADY
handling. The seen_valid_ready flag is cleared to indicate that only AWREADY has been
asserted.
handle_write_addr_ready()
// Task : handle_write_addr_ready
// This method assert/de-assert the write address channel ready signal.
// Assertion and de-assertion is done based on m_wr_addr_phase_ready_delay
task automatic handle_write_addr_ready;
bit seen_valid_ready;
int tmp_ready_delay;
int tmp_config_num_outstanding_wr_phase;
axi4_slave_ready_delay_mode_e tmp_mode;
forever
begin
tmp_config_num_outstanding_wr_phase = bfm.get_config
(AXI4_CONFIG_NUM_OUTSTANDING_WR_PHASE);
while
(
(tmp_config_num_outstanding_wr_phase >=
m_max_outstanding_write_trans) &&
(m_max_outstanding_write_trans > 0)
)
begin
bfm.wait_on(AXI4_CLOCK_POSEDGE);
tmp_config_num_outstanding_wr_phase = bfm.get_config
(AXI4_CONFIG_NUM_OUTSTANDING_WR_PHASE);
end
wait(m_wr_addr_phase_ready_delay > 0);
tmp_ready_delay = m_wr_addr_phase_ready_delay;
tmp_mode = slave_ready_delay_mode;
if (tmp_mode == AXI4_VALID2READY)
begin
fork
bfm.execute_write_addr_ready(1'b0);
join_none
bfm.get_write_addr_cycle;