Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 55)

SystemVerilog AXI3 and AXI4 Master BFMs
Master Assertions
Mentor VIP AE AXI3/4 User Guide, V10.2b 37
September 2013
1.
Refer to Master Timing and Events for details of simulator time-steps.
Master Assertions
Each master BFM performs protocol error checking using the built-in assertions.
Note
The built-in BFM assertions are independent of programming language and simulator.
AXI3 Assertion Configuration
By default, all built-in assertions are enabled in the master BFM. To globally disable them in the
master BFM, use the
set_config() command as the following example illustrates:
Slave Attributes
**_CONFIG_SUPPORT_EXCLUSIVE_ACCESS Configures the support for an exclusive
slave. If enabled the BFM will expect
an EXOKAY response to a successful
exclusive transaction. If disabled the
BFM will expect an OKAY response to
an exclusive transaction. Refer to the
AMBA AXI protocol specification for
more details.
0 = disabled
1 = enabled (default)
AXI_CONFIG_SLAVE_DEFAULT_UNDER_RESET (AXI3) The slave BFM drives the
BVALID and RVALID signals low
during reset. Refer to the AMBA AXI
Protocol specification for more details.
0 = false (default)
1 = true
**_CONFIG_SLAVE_START_ADDR Configures the start address map for
the slave.
**_CONFIG_SLAVE_END_ADDR Configures the end address map for
the slave.
**_CONFIG_READ_DATA_REORDERING_DEPTH The slave read reordering depth. Refer
to the AMBA AXI Protocol specification
for more details. Default: 1.
Error Detection
**_CONFIG_ENABLE_ALL_ASSERTIONS Global enable/disable of all assertion
checks in the BFM.
0 = disabled
1 = enabled (default)
**_CONFIG_ENABLE_ASSERTION Individual enable/disable of assertion
check in the BFM.
0 = disabled
1 = enabled (default)
Table 3-2. Master BFM Configuration (cont.)