Handle_read_data_ready, Example 11-15. process handle_write_resp_ready, As shown in the – Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM User Manual
Page 641: Example 11-15
VHDL Tutorials
Verifying a Slave DUT
Mentor VIP AE AXI3/4 User Guide, V10.2b
621
September 2013
The BREADY signal is deasserted using the nonblocking call to the
procedure and waits for a write channel response phase to occur with a call to the blocking
procedure. A received write response phase indicates that the
BVALID signal has been asserted, triggering the starting point for the delay of the BREADY
signal. In a loop it delays the assertion of BREADY based on the setting of the
variable. After the delay, another call to the
procedure to assert the BREADY signal completes the BREADY
handling.
Example 11-15. Process handle_write_resp_ready
-- handle_write_resp_ready : write response ready through path 5.
-- This method assert/de-assert the write response channel ready signal.
-- Assertion and de-assertion is done based on following variable's value:
-- m_wr_resp_phase_ready_delay
process
variable tmp_ready_delay : integer;
begin
wait_on(AXI4_RESET_0_TO_1, index, AXI4_PATH_5, axi4_tr_if_5(index));
wait_on(AXI4_CLOCK_POSEDGE, index, AXI4_PATH_5, axi4_tr_if_5(index));
loop
wait until m_wr_resp_phase_ready_delay > 0;
tmp_ready_delay := m_wr_resp_phase_ready_delay;
execute_write_resp_ready(0, 1, index, AXI4_PATH_5,
axi4_tr_if_5(index));
get_write_response_cycle(index, AXI4_PATH_5, axi4_tr_if_5(index));
if(tmp_ready_delay > 1) then
for i in 0 to tmp_ready_delay-2 loop
wait_on(AXI4_CLOCK_POSEDGE, index, AXI4_PATH_5,
axi4_tr_if_5(index));
end loop;
end if;
execute_write_resp_ready(1, 1, index, AXI4_PATH_5,
axi4_tr_if_5(index));
end loop;
wait;
end process;
handle_read_data_ready
The handle read data ready process handles the RREADY signal for the read data channel. It
delays the assertion of the RREADY signal based on the setting of the
variable. The whole process runs concurrently with other
processes in the test program, using the path_id = AXI4_PATH_6 (see
for details of path_id), and is similar in operation to the
procedure. Refer to the
“VHDL AXI4 Master BFM Test Program”
page 743 for the complete handle_read_data_ready code listing.