Table 8-2. master bfm configuration – Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM User Manual
Page 223
VHDL AXI3 and AXI4 Master BFMs
Master BFM Configuration
Mentor VIP AE AXI3/4 User Guide, V10.2b
205
September 2013
A master BFM has configuration fields that you can set via the
function to
configure timeout factors, slave exclusive support, setup and hold times, etc. You can also get
the value of a configuration field via the
procedures. The full list of configuration
fields is described in
below.
**_RDATA_WIDTH
Read data signal width in bits. This applies to the RDATA
signals. Refer to the AMBA AXI Protocol specification for more
details. Default: 64.
**_WDATA_WIDTH
Write data signal width in bits. This applies to the WDATA
signals. Refer to the AMBA AXI Protocol specification for more
details. Default: 64.
**_ID_WIDTH
ID signal width in bits. This applies to the RID and WID signals.
Refer to the AMBA AXI Protocol specification for more details.
Default: 4.
AXI4_USER_WIDTH
(AXI4) User data signal width in bits. This applies to the
ARUSER, AWUSER, RUSER, WUSER and BUSER signals.
Refer to the AMBA AXI Protocol specification for more details.
Default: 8.
AXI4_REGION_MAP_SIZE
(AXI4) Region signal width in bits. This applies to the
ARREGION and AWREGION signals. Refer to the AMBA AXI
Protocol specification for more details. Default: 16.
Table 8-2. Master BFM Configuration
Configuration Field
Description
Timing Variables
**_CONFIG_SETUP_TIME
The setup-time prior to the active edge of
ACLK, in units of simulator time-steps for all
signals.
1
Default: 0.
**_CONFIG_HOLD_TIME
The hold-time after the active edge of
ACLK, in units of simulator time-steps for all
signals.
1
Default: 0.
**_CONFIG_MAX_TRANSACTION_TIME_FACTOR
The maximum timeout duration for a
read/write transaction in clock cycles.
Default: 100000.
AXI_CONFIG_TIMEOUT_MAX_DATA_TRANSFER
(AXI3) The maximum number of write data
beats that the AXI3 BFM can generate as
part of write data burst of write transfer.
Default: 1024.
**_CONFIG_BURST_TIMEOUT_FACTOR
The maximum delay between the individual
phases of a read/write transaction in clock
cycles. Default: 10000.
**_CONFIG_MAX_LATENCY_AWVALID_
ASSERTION_TO_AWREADY
The maximum timeout duration from the
assertion of AWVALID to the assertion of
AWREADY in clock periods (default
10000).
Table 8-1. Master BFM Signal Width Parameters