Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 197)

SystemVerilog Tutorials
Verifying a Master DUT
Mentor VIP AE AXI3/4 User Guide, V10.2b 179
September 2013
Example 6-44. handle_read
// Task : handle_read
// This method reads data from memory and send read data/response
// either at burst or phase level depending upon slave working
// mode.
task automatic handle_read(input axi4_transaction read_trans);
addr_t addr[];
bit [7:0] mem_data[];
set_read_data_valid_delay(read_trans);
for(int i = 0; bfm.get_read_addr(read_trans, i, addr); i++)
begin
mem_data = new[addr.size()];
for (int j = 0; j < addr.size(); j++)
mem_data[j] = do_byte_read(addr[j]);
bfm.set_read_data(read_trans, i, addr, mem_data);
if (slave_mode == AXI4_PHASE_SLAVE)
bfm.execute_read_data_phase(read_trans, i);
end
if (slave_mode == AXI4_TRANSACTION_SLAVE)
bfm.execute_read_data_burst(read_trans);
endtask