Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 696)

Mentor VIP AE AXI3/4 User Guide, V10.2b 676
Assertions
AXI3 Assertions
September 2013
Error
Code Error Name Description Property
Ref
AXI3-
60160 AXI_FIRST_DATA_ITEM_OF_
TRANSACTION_WRITE_ORDER_
VIOLATION The order in which a slave receives the first
data item of each transaction must be the
same as the order in which it receives the
addresses for the transaction. A5.3.3
AXI3-
60161 AXI_AWLEN_MISMATCHED_WITH_
COMPLETED_WRITE_DATA_BURST Actual length of data burst has exceeded the
burst length specified by AWLEN. A3.4.1
AXI3-
60162 AXI_WRITE_LENGTH_MISMATCHED_
ACTUAL_LENGTH_OF_WRITE_
DATA_BURST_EXCEEDS_AWLEN AWLEN value of write address control does
not match with corresponding outstanding
write data burst length. A3.4.1
AXI3-
60163 AXI_AWLEN_MISMATCHED_ACTUAL_
LENGTH_OF_WRITE_DATA_BURST_
EXCEEDS_AWLEN The actual length of write data burst exceeds
with the length specified by AWLEN. A3.4.1
AXI3-
60164 AXI_WLAST_ASSERTED_DURING_
DATA_PHASE_OTHER_THAN_LAST WLAST must only be asserted during the last
data phase. A3.4.1
AXI3-
60165 AXI_WRITE_INTERLEAVE_DEPTH_
VIOLATION Write data bursts should not be interleaved
beyond the write interleaving depth. A5.3.3
AXI3-
60166 AXI_WRITE_RESPONSE_
WITHOUT_ADDR Write response should not be sent before the
corresponding address has completed. A3.3.1
AXI3-
60167 AXI_WRITE_RESPONSE_
WITHOUT_DATA Write response should not be sent before the
corresponding write data burst has
completed. A3.3.1
AXI3-
60168 AXI_AWVALID_HIGH_DURING_RESET AWVALID asserted during the reset state. A3.1.2
AXI3-
60169 AXI_WVALID_HIGH_DURING_RESET WVALID asserted during the reset state A3.1.2
AXI3-
60170 AXI_BVALID_HIGH_DURING_RESET BVALID asserted during the reset state A3.1.2
AXI3-
60171 AXI_ARVALID_HIGH_DURING_RESET ARVALID asserted during the reset state A3.1.2
AXI3-
60172 AXI_RVALID_HIGH_DURING_RESET RVALID asserted during the reset state A3.1.2
AXI3-
60173 AXI_RLAST_VIOLATION RLAST signal should be asserted along with
the final transfer of the read data burst. A3.4.1
AXI3-
60174 AXI_EX_WRITE_AFTER_
EX_READ_FAILURE It is recommended that an exclusive write
access should not be performed after the
corresponding exclusive read failure. A7.2.2
AXI3-
60175 AXI_TIMEOUT_WAITING_FOR_
WRITE_DATA Timed-out waiting for a data phase in write
data burst. A2.3
Table A-1. AXI3 Assertions (cont.)