Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 16)

Mentor VIP AE AXI3/4 User Guide, V10.2b 16
September 2013
List of Figures
Figure 1-1. Execute Write Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 1-2. Master Write Transaction Phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 1-3. Slave Write Transaction Phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 1-4. Master Read Transaction Phases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 1-5. Slave Read Transaction Phases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 2-1. SystemVerilog BFM Internal Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 2-2. Valid Data on Byte Lanes During a Write Transaction . . . . . . . . . . . . . . . . . . . 26
Figure 2-3. Operational Transaction Field delay_mode = AXI_VALID2READY
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 2-4. Operational Transaction Field delay_mode = AXI_TRANS2READY
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 5-1. Inline Monitor Connection Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 6-1. Slave DUT Top-level Testbench Environment. . . . . . . . . . . . . . . . . . . . . . . . . . 137
Figure 6-2. master_ready_delay_mode = AXI4_VALID2READY . . . . . . . . . . . . . . . . . . . 144
Figure 6-3. master_ready_delay_mode = AXI4_TRANS2READY . . . . . . . . . . . . . . . . . . . 145
Figure 6-4. Master DUT Top-level Testbench Environment. . . . . . . . . . . . . . . . . . . . . . . . . 155
Figure 6-5. Slave Test Program Advanced API Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Figure 6-6. slave_ready_delay_mode = AXI4_VALID2READY . . . . . . . . . . . . . . . . . . . . 172
Figure 6-7. slave_ready_delay_mode = AXI4_TRANS2READY . . . . . . . . . . . . . . . . . . . . 172
Figure 6-8. Slave Test Program Advanced API Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Figure 7-1. VHDL BFM Internal Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Figure 7-2. Valid Data on Byte Lanes During a Write Transaction . . . . . . . . . . . . . . . . . . . 198
Figure 10-1. Inline Monitor Connection Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
Figure 11-1. Slave DUT Top-level Testbench Environment. . . . . . . . . . . . . . . . . . . . . . . . . 607
Figure 11-2. Master DUT Top-level Testbench Environment. . . . . . . . . . . . . . . . . . . . . . . . 622
Figure 11-3. Slave Test Program Advanced API Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631
Figure 11-4. Slave Test Program Advanced API Processes . . . . . . . . . . . . . . . . . . . . . . . . . 644
Figure 12-1. Copy the Contents of qsys-examples from the Installation Folder . . . . . . . . . . 654
Figure 12-2. Paste qsys-examples From Installation to Work Folder . . . . . . . . . . . . . . . . . . 655
Figure 12-3. Select Qsys from the Quartus II Software Top-Level Menu . . . . . . . . . . . . . . 656
Figure 12-4. Open the ex1_back_to_back_sv.qsys Example . . . . . . . . . . . . . . . . . . . . . . . . . 656
Figure 12-5. Quartus II Software Displays Connectivity of the Example . . . . . . . . . . . . . . 657
Figure 12-6. Generation Tab Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657
Figure 12-7. Set Path, Simulation and Synthesis Options . . . . . . . . . . . . . . . . . . . . . . . . . . 658
Figure 12-8. Click Generate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659
Figure 12-9. Select the Work Directory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660