Set_data_ready_delay(), Axi3 example, Axi4 bfm – Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM User Manual
Page 446

Mentor VIP AE AXI3/4 User Guide, V10.2b
426
VHDL AXI3 and AXI4 Slave BFMs
set_data_ready_delay()
September 2013
set_data_ready_delay()
This AXI3 nonblocking procedure sets the data_ready_delay field for a transaction that is
uniquely identified by the transaction_id field previously created by
AXI3 Example
-- Create a slave transaction. Creation returns tr_id to identify
-- the transaction.
create_slave_transaction(tr_id, bfm_index, axi_tr_if_0(bfm_index));
-- Set the write data channel WREADY delay to 3 ACLK cycles for the first
-- dataphase (beat) of the tr_id transaction.
set_data_ready_delay(3, 0, tr_id, bfm_index, axi_tr_if_0(bfm_index));
-- Set the write data channel WREADY delay to 2 ACLK cycles for the second
-- data phase (beat) of the tr_id transaction.
set_data_ready_delay(2, 1, tr_id, bfm_index, axi_tr_if_0(bfm_index));
AXI4 BFM
Note
This procedure is not supported in the AXI4 BFM API.
Prototype
set_data_ready_delay
(
data_ready_delay: in integer;
index : in integer; --optional
transaction_id : in integer;
bfm_id : in integer;
path_id : in axi_path_t; --optional
signal tr_if : inout axi_vhd_if_struct_t
);
Arguments
data_ready_delay
Write data channel array to hold WREADY delays measured in
ACLK cycles for this transaction. Default: 0.
index
(Optional) Array element number for data_ready_delay.
transaction_id
Transaction identifier. Refer to
on page 203 for more details.
bfm_id
on page 203 for more details.
path_id
(Optional) Parallel process path identifier:
AXI_PATH_0
AXI_PATH_1
AXI_PATH_2
AXI_PATH_3
AXI_PATH_4
“Overloaded Procedure Common Arguments”
page 203 for more details.
tr_if
Transaction signal interface. Refer to
on page 203 for more details.
Returns
None