Example 6-25. slave_mode, Slave_mode – Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM User Manual
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Mentor VIP AE AXI3/4 User Guide, V10.2b
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SystemVerilog Tutorials
Verifying a Master DUT
September 2013
There is a
transaction field that you can configure to control the behavior of reading
and writing to the
. It has two modes AXI_TRANSACTION_SLAVE and
AXI_PHASE_SLAVE.
Example 6-25. slave_mode
// Enum type for slave mode
// AXI_TRANSACTION_SLAVE - Works at burst level (write data is received at
// burst and read data/response is sent in burst)
// AXI_PHASE_SLAVE - Write data and read data/response is serviced
// at phase level
typedef enum bit
{
AXI_TRANSACTION_SLAVE = 1'b0,
AXI_PHASE_SLAVE = 1'b1
} axi_slave_mode_e;
// Slave mode selection : Default is transaction-level slave
axi_slave_mode_e slave_mode = AXI_TRANSACTION_SLAVE;
The default AXI_TRANSACTION_SLAVE mode “saves up” an entire data burst and modifies
the Slave Test Program internal memory in zero time for the whole burst. Therefore, a read from
internal memory is buffered at the beginning of the read burst for the whole burst. The buffered
read data is then transmitted over the protocol signals to the master on a phase-by-phase (beat-
by-beat) basis. For a write, the write data burst is buffered on a phase-by-phase (beat-by-beat)
basis for the whole burst. Only at the end of the write burst are the buffered contents written to
the internal memory.
The AXI_PHASE_SLAVE mode changes the Slave Test Program internal memory on each data
phase (beat). Therefore, a read from the internal memory occurs only when the read data phase
(beat) actually starts on the protocol signals. For a write, data is written to the internal memory
as soon as each individual write data phase (beat) completes.
Note
In addition to the above functions, you can configure other aspects of the AXI3 Slave
BFM by using the functions: