Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 171)

SystemVerilog Tutorials
Verifying a Slave DUT
Mentor VIP AE AXI3/4 User Guide, V10.2b 153
September 2013
If the master_delay_ready_mode = AXI4_TRANS2READY, then a check of the
seen_valid_ready flag is performed to indicate that a previous write transaction has completed.
If a write transaction is still active (indicated by either BVALID or BREADY not asserted) then
the code waits until the previous write transaction has completed. The BREADY signal is
deasserted using the nonblocking call to the
execute_write_resp_ready() task and waits for the
number of ACLK cycles defined by m_wr_resp_phase_ready_delay . A nonblocking call to the
execute_write_resp_ready() task to assert the BREADY signal completes the BREADY handling.
The seen_valid_ready flag is cleared to indicate that only BREADY has been asserted.