Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 51)

Mentor VIP AE AXI3/4 User Guide, V10.2b 33
September 2013
Chapter 3
SystemVerilog AXI3 and AXI4 Master BFMs
This section provides information about the SystemVerilog AXI3 and AXI4 master BFMs.
Each BFM has an API that contains tasks and functions to configure the BFM and to access the
dynamic
Transaction Record during the lifetime of the transaction.
Note
Due to AXI3 protocol specification changes, for some BFM tasks, you reference the
AXI3 BFM by specifying AXI instead of AXI3.
Master BFM Protocol Support
The AXI3 master BFM supports the AMBA AXI3 protocol with restrictions described in
“Protocol Restrictions” on page 1. In addition to the standard protocol, it supports user sideband
signals AWUSER and ARUSER.
The AXI4 master BFM supports the AMBA AXI4 protocol with restrictions described in
“Protocol Restrictions” on page 1.
Master Timing and Events
For detailed timing diagrams of the protocol bus activity, refer to the relevant AMBA AXI
protocol specification chapter, which you can use to reference details of the following master
BFM API timing and events.
The AMBA AXI protocol specification does not define any timescale or clock period with
signal events sampled and driven at rising ACLK edges. Therefore, the master BFM does not
contain any timescale, timeunit, or timeprecision declarations with the signal setup and hold
times specified in units of simulator time-steps.
The simulator time-step resolves to the smallest of all the time-precision declarations in the
testbench and design IP as a result of these directives, declarations, options, or initialization
files:
•
` timescale directives in design elements.
•
timeprecision declarations in design elements.
•
compiler command-line options.
•
simulation command-line options.