Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 657)

VHDL Tutorials
Verifying a Master DUT
Mentor VIP AE AXI3/4 User Guide, V10.2b 637
September 2013
AXI4 BFM Slave Test Program
The Slave Test Program is a memory model that contains two APIs: an AXI4 Basic Slave API
Definition and an AXI4 Advanced Slave API Definition .
The AXI4 Basic Slave API Definition allows you to create a wide range of stimulus scenarios to
test a master DUT. This API definition simplifies the creation of slave stimulus based on the
default response of OKAY to master read and write transactions.
The AXI4 Advanced Slave API Definition allows you to create additional response scenarios to
transactions. For example, a successful exclusive transaction requires an EXOKAY response.
For a complete code listing of the slave test program, refer to “SystemVerilog AXI4 Slave BFM
Test Program” on page 720 .
AXI4 Basic Slave API Definition
The Basic Slave Test Program API contains:
•
Procedures m_wr_addr_phase_ready_delay and do_byte_write() that read and write a
byte of data to Internal Memory , respectively.
•
Procedures set_read_data_valid_delay() and set_wr_resp_valid_delay() to configure
the delay of the read data channel RVALID, and write response channel BVALID signals,
respectively.
•
Variables m_wr_addr_phase_ready_delay and m_rd_addr_phase_ready_delay to
configure the delay of the read/write address channel AWVALID/ARVALID signals, and
m_wr_data_phase_ready_delay to configure the delay of the write response channel
BVALID signal
•
A slave_mode variable that configures the behavior of reading and writing to internal
memory.
Configuration variables m_max_outstanding_read_trans and m_max_outstanding_write_trans
back-pressure a master from transmitting additional read and write transactions when the
configured value has been reached.
•
Internal Memory
The internal memory for the slave is defined as an array of 8-bits, so that each byte of data is
stored as an address/data pair.